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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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net: mdio-octeon: Modify driver to work on both ThunderX and Octeon
This patch modifies the mdio-octeon driver to work on both ThunderX and Octeon SoCs from Cavium Inc. Signed-off-by: Sunil Goutham <sgoutham@cavium.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Radha Mohan Chintakuntla
David S. Miller
parent
71382bc043
commit
a6d6786452
@ -150,13 +150,13 @@ config MDIO_GPIO
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will be called mdio-gpio.
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config MDIO_OCTEON
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tristate "Support for MDIO buses on Octeon SOCs"
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depends on CAVIUM_OCTEON_SOC
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default y
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tristate "Support for MDIO buses on Octeon and ThunderX SOCs"
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depends on 64BIT
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help
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This module provides a driver for the Octeon MDIO busses.
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It is required by the Octeon Ethernet device drivers.
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This module provides a driver for the Octeon and ThunderX MDIO
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busses. It is required by the Octeon and ThunderX ethernet device
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drivers.
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If in doubt, say Y.
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@ -7,6 +7,7 @@
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*/
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_mdio.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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@ -14,11 +15,12 @@
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#include <linux/phy.h>
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#include <linux/io.h>
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#ifdef CONFIG_CAVIUM_OCTEON_SOC
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-smix-defs.h>
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#endif
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#define DRV_VERSION "1.0"
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#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
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#define DRV_VERSION "1.1"
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#define DRV_DESCRIPTION "Cavium Networks Octeon/ThunderX SMI/MDIO driver"
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#define SMI_CMD 0x0
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#define SMI_WR_DAT 0x8
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@ -26,6 +28,79 @@
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#define SMI_CLK 0x18
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#define SMI_EN 0x20
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#ifdef __BIG_ENDIAN_BITFIELD
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#define OCT_MDIO_BITFIELD_FIELD(field, more) \
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field; \
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more
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#else
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#define OCT_MDIO_BITFIELD_FIELD(field, more) \
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more \
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field;
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#endif
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union cvmx_smix_clk {
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u64 u64;
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struct cvmx_smix_clk_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
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OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
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OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
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OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
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OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
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OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
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OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
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OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
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;))))))))))
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} s;
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};
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union cvmx_smix_cmd {
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u64 u64;
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struct cvmx_smix_cmd_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
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OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
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OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
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;))))))
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} s;
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};
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union cvmx_smix_en {
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u64 u64;
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struct cvmx_smix_en_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
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OCT_MDIO_BITFIELD_FIELD(u64 en:1,
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;))
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} s;
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};
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union cvmx_smix_rd_dat {
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u64 u64;
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struct cvmx_smix_rd_dat_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
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OCT_MDIO_BITFIELD_FIELD(u64 val:1,
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OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
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;))))
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} s;
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};
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union cvmx_smix_wr_dat {
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u64 u64;
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struct cvmx_smix_wr_dat_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
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OCT_MDIO_BITFIELD_FIELD(u64 val:1,
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OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
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;))))
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} s;
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};
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enum octeon_mdiobus_mode {
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UNINIT = 0,
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C22,
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@ -41,6 +116,21 @@ struct octeon_mdiobus {
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int phy_irq[PHY_MAX_ADDR];
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};
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#ifdef CONFIG_CAVIUM_OCTEON_SOC
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static void oct_mdio_writeq(u64 val, u64 addr)
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{
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cvmx_write_csr(addr, val);
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}
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static u64 oct_mdio_readq(u64 addr)
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{
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return cvmx_read_csr(addr);
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}
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#else
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#define oct_mdio_writeq(val, addr) writeq_relaxed(val, (void *)addr)
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#define oct_mdio_readq(addr) readq_relaxed((void *)addr)
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#endif
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static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
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enum octeon_mdiobus_mode m)
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{
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@ -49,10 +139,10 @@ static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
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if (m == p->mode)
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return;
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smi_clk.u64 = cvmx_read_csr(p->register_base + SMI_CLK);
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smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
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smi_clk.s.mode = (m == C45) ? 1 : 0;
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smi_clk.s.preamble = 1;
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cvmx_write_csr(p->register_base + SMI_CLK, smi_clk.u64);
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oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
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p->mode = m;
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}
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@ -67,7 +157,7 @@ static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
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smi_wr.u64 = 0;
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smi_wr.s.dat = regnum & 0xffff;
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cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
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oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
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regnum = (regnum >> 16) & 0x1f;
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@ -75,14 +165,14 @@ static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
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smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
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oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
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smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
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} while (smi_wr.s.pending && --timeout);
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if (timeout <= 0)
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@ -114,14 +204,14 @@ static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
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smi_cmd.s.phy_op = op;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
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oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT);
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smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
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} while (smi_rd.s.pending && --timeout);
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if (smi_rd.s.val)
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@ -153,20 +243,20 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
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smi_wr.u64 = 0;
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smi_wr.s.dat = val;
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cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
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oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = op;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
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oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
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smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
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} while (smi_wr.s.pending && --timeout);
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if (timeout <= 0)
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@ -210,7 +300,7 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
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smi_en.u64 = 0;
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smi_en.s.en = 1;
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cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
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oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
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bus->mii_bus->priv = bus;
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bus->mii_bus->irq = bus->phy_irq;
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@ -234,7 +324,7 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
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mdiobus_free(bus->mii_bus);
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fail:
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smi_en.u64 = 0;
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cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
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oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
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return err;
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}
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@ -248,7 +338,7 @@ static int octeon_mdiobus_remove(struct platform_device *pdev)
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mdiobus_unregister(bus->mii_bus);
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mdiobus_free(bus->mii_bus);
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smi_en.u64 = 0;
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cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
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oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
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return 0;
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}
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