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drm/i915/fbc: Store the fbc1 compression interval in the params

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Avoid the FBC_CONTROL rmw and just store the fbc compression
interval in the params/

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200429101034.8208-10-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
This commit is contained in:
Ville Syrjälä 2020-04-29 13:10:31 +03:00
parent a4c74b2974
commit a68ce21ba0
2 changed files with 8 additions and 7 deletions
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13
drivers/gpu/drm/i915/display/intel_fbc.c
View File

@ -132,8 +132,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
}
/* enable it... */
fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
fbc_ctl &= FBC_CTL_INTERVAL(0x3fff);
fbc_ctl = FBC_CTL_INTERVAL(params->interval);
fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
if (IS_I945GM(dev_priv))
fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
@ -699,6 +698,9 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->fb.stride = fb->pitches[0];
cache->fb.modifier = fb->modifier;
/* This value was pulled out of someone's hat */
cache->interval = 500;
cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
@ -873,6 +875,8 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
params->fence_id = cache->fence_id;
params->fence_y_offset = cache->fence_y_offset;
params->interval = cache->interval;
params->crtc.pipe = crtc->pipe;
params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
@ -1420,11 +1424,6 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
return;
}
/* This value was pulled out of someone's hat */
if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
intel_de_write(dev_priv, FBC_CONTROL,
FBC_CTL_INTERVAL(500));
/* We still don't have any sort of hardware state readout for FBC, so
* deactivate it in case the BIOS activated it to make sure software
* matches the hardware state. */

2
drivers/gpu/drm/i915/i915_drv.h
View File

@ -422,6 +422,7 @@ struct intel_fbc {
unsigned int fence_y_offset;
u16 gen9_wa_cfb_stride;
u16 interval;
s8 fence_id;
} state_cache;
@ -446,6 +447,7 @@ struct intel_fbc {
int cfb_size;
unsigned int fence_y_offset;
u16 gen9_wa_cfb_stride;
u16 interval;
s8 fence_id;
bool plane_visible;
} params;