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arm64: dts: r8a7796: Add CA53 L2 cache-controller node

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Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Extracted from a patch by Takeshi Kihara in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2017-03-07 19:03:24 +01:00 committed by Simon Horman
parent 9fccf4d610
commit a681e6d632
1 changed files with 7 additions and 0 deletions
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arch/arm64/boot/dts/renesas/r8a7796.dtsi
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@ -61,6 +61,13 @@ L2_CA57: cache-controller-0 {
cache-unified;
cache-level = <2>;
};
L2_CA53: cache-controller-1 {
compatible = "cache";
power-domains = <&sysc R8A7796_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
};
extal_clk: extal {