mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 20:16:44 +07:00
ARM: shmobile: Break out R-Car SYSC PM code
Break out the R-Car SYSC power management code from the r8a7779 SoC code. With this new shared R-Car SYSC code base it is possible to hook in Generation 2 SoCs as well. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Magnus Damm
Simon Horman
parent
4a51856b42
commit
a6557eb795
@ -52,7 +52,7 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o pm-rmobile.o
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obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o
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obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o pm-rmobile.o
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obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o pm-rcar.o
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# Board objects
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ifdef CONFIG_ARCH_SHMOBILE_MULTI
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15
arch/arm/mach-shmobile/include/mach/pm-rcar.h
Normal file
15
arch/arm/mach-shmobile/include/mach/pm-rcar.h
Normal file
@ -0,0 +1,15 @@
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#ifndef PM_RCAR_H
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#define PM_RCAR_H
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struct rcar_sysc_ch {
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unsigned long chan_offs;
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unsigned int chan_bit;
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unsigned int isr_bit;
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};
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int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch);
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int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch);
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bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch);
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void __iomem *rcar_sysc_init(phys_addr_t base);
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#endif /* PM_RCAR_H */
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@ -3,6 +3,7 @@
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#include <linux/sh_clk.h>
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#include <linux/pm_domain.h>
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#include <mach/pm-rcar.h>
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/* HPB-DMA slave IDs */
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enum {
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@ -11,18 +12,12 @@ enum {
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HPBDMA_SLAVE_SDHI0_RX,
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};
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struct r8a7779_pm_ch {
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unsigned long chan_offs;
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unsigned int chan_bit;
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unsigned int isr_bit;
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};
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struct r8a7779_pm_domain {
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struct generic_pm_domain genpd;
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struct r8a7779_pm_ch ch;
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struct rcar_sysc_ch ch;
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};
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static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
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static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d)
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{
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return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
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}
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@ -41,8 +36,6 @@ extern void r8a7779_clock_init(void);
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extern void r8a7779_pinmux_init(void);
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extern void r8a7779_pm_init(void);
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extern void r8a7779_register_twd(void);
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extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
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extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
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#ifdef CONFIG_PM
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extern void __init r8a7779_init_pm_domains(void);
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@ -20,132 +20,22 @@
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#include <linux/console.h>
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#include <asm/io.h>
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#include <mach/common.h>
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#include <mach/pm-rcar.h>
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#include <mach/r8a7779.h>
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static void __iomem *r8a7779_sysc_base;
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/* SYSC */
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#define SYSCSR 0x00
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#define SYSCISR 0x04
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#define SYSCISCR 0x08
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#define SYSCIER 0x0c
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#define SYSCIMR 0x10
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#define PWRSR0 0x40
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#define PWRSR1 0x80
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#define PWRSR2 0xc0
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#define PWRSR3 0x100
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#define PWRSR4 0x140
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#define PWRSR_OFFS 0x00
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#define PWROFFCR_OFFS 0x04
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#define PWRONCR_OFFS 0x0c
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#define PWRER_OFFS 0x14
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#define SYSCSR_RETRIES 100
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#define SYSCSR_DELAY_US 1
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#define SYSCISR_RETRIES 1000
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#define SYSCISR_DELAY_US 1
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#if defined(CONFIG_PM) || defined(CONFIG_SMP)
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static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */
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static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
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int sr_bit, int reg_offs)
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{
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int k;
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for (k = 0; k < SYSCSR_RETRIES; k++) {
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if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit))
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break;
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udelay(SYSCSR_DELAY_US);
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}
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if (k == SYSCSR_RETRIES)
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return -EAGAIN;
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iowrite32(1 << r8a7779_ch->chan_bit,
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r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs);
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return 0;
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}
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static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch)
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{
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return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS);
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}
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static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch)
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{
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return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS);
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}
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static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
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int (*on_off_fn)(struct r8a7779_pm_ch *))
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{
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unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
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unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
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unsigned int status;
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unsigned long flags;
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int ret = 0;
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int k;
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spin_lock_irqsave(&r8a7779_sysc_lock, flags);
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iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
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do {
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ret = on_off_fn(r8a7779_ch);
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if (ret)
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goto out;
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status = ioread32(r8a7779_sysc_base +
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r8a7779_ch->chan_offs + PWRER_OFFS);
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} while (status & chan_mask);
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for (k = 0; k < SYSCISR_RETRIES; k++) {
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if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask)
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break;
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udelay(SYSCISR_DELAY_US);
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}
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if (k == SYSCISR_RETRIES)
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ret = -EIO;
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iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
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out:
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spin_unlock_irqrestore(&r8a7779_sysc_lock, flags);
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pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
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r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
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ioread32(r8a7779_sysc_base + PWRSR1),
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ioread32(r8a7779_sysc_base + PWRSR2),
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ioread32(r8a7779_sysc_base + PWRSR3),
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ioread32(r8a7779_sysc_base + PWRSR4), ret);
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return ret;
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}
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int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
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{
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return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
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}
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int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
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{
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return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
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}
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static void __init r8a7779_sysc_init(void)
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{
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r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE);
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if (!r8a7779_sysc_base)
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panic("unable to ioremap r8a7779 SYSC hardware block\n");
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void __iomem *base = rcar_sysc_init(0xffd85000);
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/* enable all interrupt sources, but do not use interrupt handler */
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iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER);
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iowrite32(0, r8a7779_sysc_base + SYSCIMR);
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iowrite32(0x0131000e, base + SYSCIER);
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iowrite32(0, base + SYSCIMR);
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}
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#else /* CONFIG_PM || CONFIG_SMP */
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@ -158,24 +48,17 @@ static inline void r8a7779_sysc_init(void) {}
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static int pd_power_down(struct generic_pm_domain *genpd)
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{
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return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
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return rcar_sysc_power_down(to_r8a7779_ch(genpd));
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}
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static int pd_power_up(struct generic_pm_domain *genpd)
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{
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return r8a7779_sysc_power_up(to_r8a7779_ch(genpd));
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return rcar_sysc_power_up(to_r8a7779_ch(genpd));
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}
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static bool pd_is_off(struct generic_pm_domain *genpd)
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{
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struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd);
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unsigned int st;
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st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS);
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if (st & (1 << r8a7779_ch->chan_bit))
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return true;
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return false;
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return rcar_sysc_power_is_off(to_r8a7779_ch(genpd));
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}
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static bool pd_active_wakeup(struct device *dev)
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142
arch/arm/mach-shmobile/pm-rcar.c
Normal file
142
arch/arm/mach-shmobile/pm-rcar.c
Normal file
@ -0,0 +1,142 @@
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/*
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* R-Car SYSC Power management support
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*
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* Copyright (C) 2014 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <asm/io.h>
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#include <mach/pm-rcar.h>
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static void __iomem *rcar_sysc_base;
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/* SYSC */
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#define SYSCSR 0x00
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#define SYSCISR 0x04
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#define SYSCISCR 0x08
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#define PWRSR_OFFS 0x00
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#define PWROFFCR_OFFS 0x04
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#define PWRONCR_OFFS 0x0c
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#define PWRER_OFFS 0x14
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#define SYSCSR_RETRIES 100
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#define SYSCSR_DELAY_US 1
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#define SYSCISR_RETRIES 1000
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#define SYSCISR_DELAY_US 1
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#if defined(CONFIG_PM) || defined(CONFIG_SMP)
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static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
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static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch,
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int sr_bit, int reg_offs)
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{
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int k;
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for (k = 0; k < SYSCSR_RETRIES; k++) {
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if (ioread32(rcar_sysc_base + SYSCSR) & (1 << sr_bit))
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break;
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udelay(SYSCSR_DELAY_US);
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}
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if (k == SYSCSR_RETRIES)
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return -EAGAIN;
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iowrite32(1 << sysc_ch->chan_bit,
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rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
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return 0;
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}
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static int rcar_sysc_pwr_off(struct rcar_sysc_ch *sysc_ch)
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{
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return rcar_sysc_pwr_on_off(sysc_ch, 0, PWROFFCR_OFFS);
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}
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static int rcar_sysc_pwr_on(struct rcar_sysc_ch *sysc_ch)
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{
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return rcar_sysc_pwr_on_off(sysc_ch, 1, PWRONCR_OFFS);
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}
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static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch,
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int (*on_off_fn)(struct rcar_sysc_ch *))
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{
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unsigned int isr_mask = 1 << sysc_ch->isr_bit;
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unsigned int chan_mask = 1 << sysc_ch->chan_bit;
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unsigned int status;
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unsigned long flags;
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int ret = 0;
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int k;
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spin_lock_irqsave(&rcar_sysc_lock, flags);
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iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
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do {
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ret = on_off_fn(sysc_ch);
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if (ret)
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goto out;
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status = ioread32(rcar_sysc_base +
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sysc_ch->chan_offs + PWRER_OFFS);
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} while (status & chan_mask);
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for (k = 0; k < SYSCISR_RETRIES; k++) {
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if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
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break;
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udelay(SYSCISR_DELAY_US);
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}
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if (k == SYSCISR_RETRIES)
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ret = -EIO;
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iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
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out:
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spin_unlock_irqrestore(&rcar_sysc_lock, flags);
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pr_debug("sysc power domain %d: %08x -> %d\n",
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sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
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return ret;
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}
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int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch)
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{
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return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_off);
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}
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int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch)
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{
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return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_on);
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}
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bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch)
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{
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unsigned int st;
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st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
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if (st & (1 << sysc_ch->chan_bit))
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return true;
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return false;
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}
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void __iomem *rcar_sysc_init(phys_addr_t base)
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{
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rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
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if (!rcar_sysc_base)
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panic("unable to ioremap R-Car SYSC hardware block\n");
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return rcar_sysc_base;
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}
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#endif /* CONFIG_PM || CONFIG_SMP */
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@ -24,6 +24,7 @@
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/common.h>
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#include <mach/pm-rcar.h>
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#include <mach/r8a7779.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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@ -33,25 +34,25 @@
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#define AVECR IOMEM(0xfe700040)
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#define R8A7779_SCU_BASE 0xf0000000
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static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
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static struct rcar_sysc_ch r8a7779_ch_cpu1 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 1, /* ARM1 */
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.isr_bit = 1, /* ARM1 */
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};
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static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
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static struct rcar_sysc_ch r8a7779_ch_cpu2 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 2, /* ARM2 */
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.isr_bit = 2, /* ARM2 */
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};
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static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
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static struct rcar_sysc_ch r8a7779_ch_cpu3 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 3, /* ARM3 */
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.isr_bit = 3, /* ARM3 */
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};
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static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
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static struct rcar_sysc_ch *r8a7779_ch_cpu[4] = {
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[1] = &r8a7779_ch_cpu1,
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[2] = &r8a7779_ch_cpu2,
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[3] = &r8a7779_ch_cpu3,
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@ -67,7 +68,7 @@ void __init r8a7779_register_twd(void)
|
||||
|
||||
static int r8a7779_platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
struct r8a7779_pm_ch *ch = NULL;
|
||||
struct rcar_sysc_ch *ch = NULL;
|
||||
int ret = -EIO;
|
||||
|
||||
cpu = cpu_logical_map(cpu);
|
||||
@ -76,14 +77,14 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
|
||||
ch = r8a7779_ch_cpu[cpu];
|
||||
|
||||
if (ch)
|
||||
ret = r8a7779_sysc_power_down(ch);
|
||||
ret = rcar_sysc_power_down(ch);
|
||||
|
||||
return ret ? ret : 1;
|
||||
}
|
||||
|
||||
static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
struct r8a7779_pm_ch *ch = NULL;
|
||||
struct rcar_sysc_ch *ch = NULL;
|
||||
unsigned int lcpu = cpu_logical_map(cpu);
|
||||
int ret;
|
||||
|
||||
@ -91,7 +92,7 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
ch = r8a7779_ch_cpu[lcpu];
|
||||
|
||||
if (ch)
|
||||
ret = r8a7779_sysc_power_up(ch);
|
||||
ret = rcar_sysc_power_up(ch);
|
||||
else
|
||||
ret = -EIO;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user