mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 11:26:54 +07:00
sh: Split out system.h in to _32 and _64 variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
36bcd39dbc
commit
a62a3861e0
@ -12,60 +12,9 @@
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#include <asm/types.h>
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#include <asm/ptrace.h>
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struct task_struct *__switch_to(struct task_struct *prev,
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struct task_struct *next);
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#define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */
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/*
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* switch_to() should switch tasks to task nr n, first
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*/
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#define switch_to(prev, next, last) do { \
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struct task_struct *__last; \
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register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
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register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
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register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
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register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
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register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
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register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
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__asm__ __volatile__ (".balign 4\n\t" \
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"stc.l gbr, @-r15\n\t" \
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"sts.l pr, @-r15\n\t" \
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"mov.l r8, @-r15\n\t" \
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"mov.l r9, @-r15\n\t" \
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"mov.l r10, @-r15\n\t" \
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"mov.l r11, @-r15\n\t" \
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"mov.l r12, @-r15\n\t" \
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"mov.l r13, @-r15\n\t" \
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"mov.l r14, @-r15\n\t" \
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"mov.l r15, @r1 ! save SP\n\t" \
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"mov.l @r6, r15 ! change to new stack\n\t" \
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"mova 1f, %0\n\t" \
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"mov.l %0, @r2 ! save PC\n\t" \
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"mov.l 2f, %0\n\t" \
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"jmp @%0 ! call __switch_to\n\t" \
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" lds r7, pr ! with return to new PC\n\t" \
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".balign 4\n" \
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"2:\n\t" \
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".long __switch_to\n" \
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"1:\n\t" \
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"mov.l @r15+, r14\n\t" \
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"mov.l @r15+, r13\n\t" \
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"mov.l @r15+, r12\n\t" \
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"mov.l @r15+, r11\n\t" \
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"mov.l @r15+, r10\n\t" \
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"mov.l @r15+, r9\n\t" \
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"mov.l @r15+, r8\n\t" \
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"lds.l @r15+, pr\n\t" \
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"ldc.l @r15+, gbr\n\t" \
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: "=z" (__last) \
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: "r" (__ts1), "r" (__ts2), "r" (__ts4), \
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"r" (__ts5), "r" (__ts6), "r" (__ts7) \
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: "r3", "t"); \
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last = __last; \
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} while (0)
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#ifdef CONFIG_CPU_SH4A
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#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
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#define __icbi() \
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{ \
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unsigned long __addr; \
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@ -91,7 +40,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
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* Historically we have only done this type of barrier for the MMUCR, but
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* it's also necessary for the CCR, so we make it generic here instead.
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*/
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#ifdef CONFIG_CPU_SH4A
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#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
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#define mb() __asm__ __volatile__ ("synco": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("synco": : :"memory")
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@ -119,42 +68,6 @@ struct task_struct *__switch_to(struct task_struct *prev,
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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/*
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* Jump to P2 area.
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* When handling TLB or caches, we need to do it from P2 area.
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*/
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#define jump_to_P2() \
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do { \
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unsigned long __dummy; \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"or %1, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy) \
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: "r" (0x20000000)); \
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} while (0)
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/*
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* Back to P1 area.
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*/
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#define back_to_P1() \
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do { \
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unsigned long __dummy; \
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ctrl_barrier(); \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy)); \
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} while (0)
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static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
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{
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unsigned long flags, retval;
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@ -281,4 +194,10 @@ asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5,
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#define arch_align_stack(x) (x)
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#ifdef CONFIG_SUPERH32
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# include "system_32.h"
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#else
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# include "system_64.h"
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#endif
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#endif
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97
include/asm-sh/system_32.h
Normal file
97
include/asm-sh/system_32.h
Normal file
@ -0,0 +1,97 @@
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#ifndef __ASM_SH_SYSTEM_32_H
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#define __ASM_SH_SYSTEM_32_H
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#include <linux/types.h>
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struct task_struct *__switch_to(struct task_struct *prev,
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struct task_struct *next);
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/*
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* switch_to() should switch tasks to task nr n, first
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*/
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#define switch_to(prev, next, last) \
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do { \
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register u32 *__ts1 __asm__ ("r1") = &prev->thread.sp; \
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register u32 *__ts2 __asm__ ("r2") = &prev->thread.pc; \
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register u32 *__ts4 __asm__ ("r4") = (u32 *)prev; \
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register u32 *__ts5 __asm__ ("r5") = (u32 *)next; \
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register u32 *__ts6 __asm__ ("r6") = &next->thread.sp; \
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register u32 __ts7 __asm__ ("r7") = next->thread.pc; \
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struct task_struct *__last; \
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\
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__asm__ __volatile__ ( \
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".balign 4\n\t" \
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"stc.l gbr, @-r15\n\t" \
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"sts.l pr, @-r15\n\t" \
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"mov.l r8, @-r15\n\t" \
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"mov.l r9, @-r15\n\t" \
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"mov.l r10, @-r15\n\t" \
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"mov.l r11, @-r15\n\t" \
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"mov.l r12, @-r15\n\t" \
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"mov.l r13, @-r15\n\t" \
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"mov.l r14, @-r15\n\t" \
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"mov.l r15, @r1\t! save SP\n\t" \
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"mov.l @r6, r15\t! change to new stack\n\t" \
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"mova 1f, %0\n\t" \
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"mov.l %0, @r2\t! save PC\n\t" \
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"mov.l 2f, %0\n\t" \
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"jmp @%0\t! call __switch_to\n\t" \
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" lds r7, pr\t! with return to new PC\n\t" \
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".balign 4\n" \
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"2:\n\t" \
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".long __switch_to\n" \
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"1:\n\t" \
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"mov.l @r15+, r14\n\t" \
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"mov.l @r15+, r13\n\t" \
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"mov.l @r15+, r12\n\t" \
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"mov.l @r15+, r11\n\t" \
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"mov.l @r15+, r10\n\t" \
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"mov.l @r15+, r9\n\t" \
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"mov.l @r15+, r8\n\t" \
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"lds.l @r15+, pr\n\t" \
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"ldc.l @r15+, gbr\n\t" \
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: "=z" (__last) \
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: "r" (__ts1), "r" (__ts2), "r" (__ts4), \
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"r" (__ts5), "r" (__ts6), "r" (__ts7) \
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: "r3", "t"); \
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\
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last = __last; \
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} while (0)
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/*
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* Jump to P2 area.
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* When handling TLB or caches, we need to do it from P2 area.
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*/
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#define jump_to_P2() \
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do { \
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unsigned long __dummy; \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"or %1, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy) \
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: "r" (0x20000000)); \
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} while (0)
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/*
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* Back to P1 area.
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*/
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#define back_to_P1() \
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do { \
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unsigned long __dummy; \
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ctrl_barrier(); \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy)); \
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} while (0)
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#endif /* __ASM_SH_SYSTEM_32_H */
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39
include/asm-sh/system_64.h
Normal file
39
include/asm-sh/system_64.h
Normal file
@ -0,0 +1,39 @@
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#ifndef __ASM_SH_SYSTEM_64_H
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#define __ASM_SH_SYSTEM_64_H
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/*
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* include/asm-sh/system_64.h
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003 Paul Mundt
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* Copyright (C) 2004 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <asm/processor.h>
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/*
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* switch_to() should switch tasks to task nr n, first
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*/
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struct task_struct *sh64_switch_to(struct task_struct *prev,
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struct thread_struct *prev_thread,
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struct task_struct *next,
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struct thread_struct *next_thread);
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#define switch_to(prev,next,last) \
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do { \
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if (last_task_used_math != next) { \
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struct pt_regs *regs = next->thread.uregs; \
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if (regs) regs->sr |= SR_FD; \
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} \
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last = sh64_switch_to(prev, &prev->thread, next, \
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&next->thread); \
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} while (0)
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/* No segmentation.. */
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#define jump_to_P2() do { } while (0)
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#define back_to_P1() do { } while (0)
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#endif /* __ASM_SH_SYSTEM_64_H */
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@ -1,190 +0,0 @@
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#ifndef __ASM_SH64_SYSTEM_H
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#define __ASM_SH64_SYSTEM_H
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* include/asm-sh64/system.h
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003 Paul Mundt
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* Copyright (C) 2004 Richard Curnow
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*
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*/
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#include <asm/registers.h>
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#include <asm/processor.h>
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/*
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* switch_to() should switch tasks to task nr n, first
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*/
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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extern struct task_struct *sh64_switch_to(struct task_struct *prev,
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struct thread_struct *prev_thread,
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struct task_struct *next,
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struct thread_struct *next_thread);
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#define switch_to(prev,next,last) \
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do {\
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if (last_task_used_math != next) {\
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struct pt_regs *regs = next->thread.uregs;\
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if (regs) regs->sr |= SR_FD;\
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}\
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last = sh64_switch_to(prev, &prev->thread, next, &next->thread);\
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} while(0)
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#define nop() __asm__ __volatile__ ("nop")
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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extern void __xchg_called_with_bad_pointer(void);
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#define mb() __asm__ __volatile__ ("synco": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("synco": : :"memory")
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#define read_barrier_depends() do { } while (0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while (0)
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#endif /* CONFIG_SMP */
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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/* Interrupt Control */
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#ifndef HARD_CLI
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#define SR_MASK_L 0x000000f0L
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#define SR_MASK_LL 0x00000000000000f0LL
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#else
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#define SR_MASK_L 0x10000000L
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#define SR_MASK_LL 0x0000000010000000LL
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#endif
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static __inline__ void local_irq_enable(void)
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{
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/* cli/sti based on SR.BL */
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unsigned long long __dummy0, __dummy1=~SR_MASK_LL;
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__asm__ __volatile__("getcon " __SR ", %0\n\t"
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"and %0, %1, %0\n\t"
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"putcon %0, " __SR "\n\t"
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: "=&r" (__dummy0)
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: "r" (__dummy1));
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}
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static __inline__ void local_irq_disable(void)
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{
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/* cli/sti based on SR.BL */
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unsigned long long __dummy0, __dummy1=SR_MASK_LL;
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__asm__ __volatile__("getcon " __SR ", %0\n\t"
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"or %0, %1, %0\n\t"
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"putcon %0, " __SR "\n\t"
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: "=&r" (__dummy0)
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: "r" (__dummy1));
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}
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#define local_save_flags(x) \
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(__extension__ ({ unsigned long long __dummy=SR_MASK_LL; \
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__asm__ __volatile__( \
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"getcon " __SR ", %0\n\t" \
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"and %0, %1, %0" \
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: "=&r" (x) \
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: "r" (__dummy));}))
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#define local_irq_save(x) \
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(__extension__ ({ unsigned long long __d2=SR_MASK_LL, __d1; \
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__asm__ __volatile__( \
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"getcon " __SR ", %1\n\t" \
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"or %1, r63, %0\n\t" \
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"or %1, %2, %1\n\t" \
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"putcon %1, " __SR "\n\t" \
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"and %0, %2, %0" \
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: "=&r" (x), "=&r" (__d1) \
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: "r" (__d2));}));
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#define local_irq_restore(x) do { \
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if ( ((x) & SR_MASK_L) == 0 ) /* dropping to 0 ? */ \
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local_irq_enable(); /* yes...re-enable */ \
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} while (0)
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#define irqs_disabled() \
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({ \
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unsigned long flags; \
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local_save_flags(flags); \
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(flags != 0); \
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})
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static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
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{
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unsigned long flags, retval;
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local_irq_save(flags);
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retval = *m;
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*m = val;
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local_irq_restore(flags);
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return retval;
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}
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static inline unsigned long xchg_u8(volatile unsigned char * m, unsigned long val)
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{
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unsigned long flags, retval;
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local_irq_save(flags);
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retval = *m;
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*m = val & 0xff;
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local_irq_restore(flags);
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return retval;
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}
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static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 4:
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return xchg_u32(ptr, x);
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break;
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case 1:
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return xchg_u8(ptr, x);
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break;
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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/* XXX
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||||
* disable hlt during certain critical i/o operations
|
||||
*/
|
||||
#define HAVE_DISABLE_HLT
|
||||
void disable_hlt(void);
|
||||
void enable_hlt(void);
|
||||
|
||||
|
||||
#define smp_mb() barrier()
|
||||
#define smp_rmb() barrier()
|
||||
#define smp_wmb() barrier()
|
||||
|
||||
#ifdef CONFIG_SH_ALPHANUMERIC
|
||||
/* This is only used for debugging. */
|
||||
extern void print_seg(char *file,int line);
|
||||
#define PLS() print_seg(__FILE__,__LINE__)
|
||||
#else /* CONFIG_SH_ALPHANUMERIC */
|
||||
#define PLS()
|
||||
#endif /* CONFIG_SH_ALPHANUMERIC */
|
||||
|
||||
#define PL() printk("@ <%s,%s:%d>\n",__FILE__,__FUNCTION__,__LINE__)
|
||||
|
||||
#define arch_align_stack(x) (x)
|
||||
|
||||
#endif /* __ASM_SH64_SYSTEM_H */
|
||||
Loading…
Reference in New Issue
Block a user