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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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qlge: Clear frame to queue routing before reset.
Not clearing the routing bits can cause frames to erroneously get routed to management processor. Signed-off-by: Ron Mercer <ron.mercer@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -3040,25 +3040,40 @@ static int ql_start_rss(struct ql_adapter *qdev)
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return status;
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}
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static int ql_clear_routing_entries(struct ql_adapter *qdev)
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{
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int i, status = 0;
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status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
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if (status)
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return status;
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/* Clear all the entries in the routing table. */
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for (i = 0; i < 16; i++) {
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status = ql_set_routing_reg(qdev, i, 0, 0);
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if (status) {
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QPRINTK(qdev, IFUP, ERR,
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"Failed to init routing register for CAM "
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"packets.\n");
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break;
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}
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}
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ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
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return status;
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}
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/* Initialize the frame-to-queue routing. */
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static int ql_route_initialize(struct ql_adapter *qdev)
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{
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int status = 0;
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int i;
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status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
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if (status)
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return status;
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/* Clear all the entries in the routing table. */
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for (i = 0; i < 16; i++) {
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status = ql_set_routing_reg(qdev, i, 0, 0);
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if (status) {
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QPRINTK(qdev, IFUP, ERR,
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"Failed to init routing register for CAM packets.\n");
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goto exit;
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}
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}
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status = ql_clear_routing_entries(qdev);
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if (status)
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goto exit;
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status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
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if (status) {
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@ -3211,9 +3226,17 @@ static int ql_adapter_reset(struct ql_adapter *qdev)
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{
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u32 value;
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int status = 0;
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unsigned long end_jiffies = jiffies +
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max((unsigned long)1, usecs_to_jiffies(30));
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unsigned long end_jiffies;
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/* Clear all the entries in the routing table. */
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status = ql_clear_routing_entries(qdev);
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if (status) {
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QPRINTK(qdev, IFUP, ERR, "Failed to clear routing bits.\n");
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return status;
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}
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end_jiffies = jiffies +
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max((unsigned long)1, usecs_to_jiffies(30));
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ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
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do {
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