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drm/amdgpu/gfx10: unlock srbm_mutex after queue programming finish
srbm_mutex is to guarantee atomicity for r/w of gfx indexed registers Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2825,7 +2825,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
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/* Init gfx ring 0 for pipe 0 */
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mutex_lock(&adev->srbm_mutex);
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gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
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mutex_unlock(&adev->srbm_mutex);
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/* Set ring buffer size */
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ring = &adev->gfx.gfx_ring[0];
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rb_bufsz = order_base_2(ring->ring_size / 8);
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@ -2863,11 +2863,11 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
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WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
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gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
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mutex_unlock(&adev->srbm_mutex);
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/* Init gfx ring 1 for pipe 1 */
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mutex_lock(&adev->srbm_mutex);
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gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
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mutex_unlock(&adev->srbm_mutex);
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ring = &adev->gfx.gfx_ring[1];
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rb_bufsz = order_base_2(ring->ring_size / 8);
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tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
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@ -2897,6 +2897,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
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WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
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gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
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mutex_unlock(&adev->srbm_mutex);
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/* Switch to pipe 0 */
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mutex_lock(&adev->srbm_mutex);
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