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drm/i915: Explain why we need to write DPLL twice
... it's because setting the Pixel Multiply bits only takes effect once the PLL is enabled and stable. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -4089,13 +4089,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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I915_WRITE(DPLL_MD(pipe), temp);
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} else {
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/* write it again -- the BIOS does, after all */
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/* The pixel multiplier can only be updated once the
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* DPLL is enabled and the clocks are stable.
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*
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* So write it again.
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*/
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I915_WRITE(dpll_reg, dpll);
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}
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/* Wait for the clocks to stabilize. */
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POSTING_READ(dpll_reg);
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udelay(150);
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}
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intel_crtc->lowfreq_avail = false;
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