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unicore32: make dma_cache_sync a no-op
unicore32 does not implement DMA_ATTR_NON_CONSISTENT allocations, so it doesn't make any sense to do any work in dma_cache_sync given that it must be a no-op when dma_alloc_attrs returns coherent memory. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
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@ -101,15 +101,6 @@ extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
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extern void __cpuc_flush_dcache_area(void *, size_t);
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extern void __cpuc_flush_kern_dcache_area(void *addr, size_t size);
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/*
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* These are private to the dma-mapping API. Do not use directly.
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* Their sole purpose is to ensure that data held in the cache
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* is visible to DMA, or data written by DMA to system memory is
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* visible to the CPU.
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*/
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extern void __cpuc_dma_clean_range(unsigned long, unsigned long);
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extern void __cpuc_dma_flush_range(unsigned long, unsigned long);
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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@ -18,9 +18,6 @@
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#include <linux/scatterlist.h>
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#include <linux/swiotlb.h>
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#include <asm/memory.h>
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#include <asm/cacheflush.h>
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extern const struct dma_map_ops swiotlb_dma_map_ops;
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static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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@ -51,20 +48,6 @@ static inline void dma_mark_clean(void *addr, size_t size) {}
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static inline void dma_cache_sync(struct device *dev, void *vaddr,
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size_t size, enum dma_data_direction direction)
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{
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unsigned long start = (unsigned long)vaddr;
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unsigned long end = start + size;
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switch (direction) {
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case DMA_NONE:
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BUG();
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL: /* writeback and invalidate */
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__cpuc_dma_flush_range(start, end);
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break;
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case DMA_TO_DEVICE: /* writeback only */
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__cpuc_dma_clean_range(start, end);
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break;
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}
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}
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#endif /* __KERNEL__ */
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@ -20,6 +20,3 @@ EXPORT_SYMBOL(cpu_dcache_clean_area);
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EXPORT_SYMBOL(cpu_set_pte);
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EXPORT_SYMBOL(__cpuc_coherent_kern_range);
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EXPORT_SYMBOL(__cpuc_dma_flush_range);
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EXPORT_SYMBOL(__cpuc_dma_clean_range);
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