AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-25 09:26:36 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

dt-bindings: fsl: Convert i.MX7ULP SIM to json-schema

Browse Source 
Convert the i.MX7ULP SIM binding to DT schema format using json-schema.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Link: https://lore.kernel.org/r/1596595841-27563-2-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Anson Huang 2020-08-05 10:50:41 +08:00 committed by Rob Herring
parent 8ba41d6bd9
commit a505e52a65
2 changed files with 38 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt
View File

@ -1,16 +0,0 @@
Freescale i.MX7ULP System Integration Module
----------------------------------------------
The system integration module (SIM) provides system control and chip configuration
registers. In this module, chip revision information is located in JTAG ID register,
and a set of registers have been made available in DGO domain for SW use, with the
objective to maintain its value between system resets.
Required properties:
- compatible: Should be "fsl,imx7ulp-sim".
- reg: Specifies base physical address and size of the register sets.
Example:
sim: sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;
};

38
Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml Normal file
View File

@ -0,0 +1,38 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX7ULP System Integration Module
maintainers:
- Anson Huang <anson.huang@nxp.com>
description: |
The system integration module (SIM) provides system control and chip configuration
registers. In this module, chip revision information is located in JTAG ID register,
and a set of registers have been made available in DGO domain for SW use, with the
objective to maintain its value between system resets.
properties:
compatible:
items:
- const: fsl,imx7ulp-sim
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;
};