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net: phy: Add Edge-rate driver for Microsemi PHYs.
Edge-rate: As system and networking speeds increase, a signal's output transition, also know as the edge rate or slew rate (V/ns), takes on greater importance because high-speed signals come with a price. That price is an assortment of interference problems like ringing on the line, signal overshoot and undershoot, extended signal settling times, crosstalk noise, transmission line reflections, false signal detection by the receiving device and electromagnetic interference (EMI) -- all of which can negate the potential gains designers are seeking when they try to increase system speeds through the use of higher performance logic devices. The fact is, faster signaling edge rates can cause a higher level of electrical noise or other type of interference that can actually lead to slower line speeds and lower maximum system frequencies. This parameter allow the board designers to change the driving strange, and thereby change the EMI behavioral. Edge-rate parameters (vddmac, edge-slowdown) get from Device Tree. Tested on Beaglebone Black with VSC 8531 PHY. Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microsemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Raju Lakkaraju
David S. Miller
parent
277964e19e
commit
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58
Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
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58
Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt
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@ -0,0 +1,58 @@
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* Microsemi - vsc8531 Giga bit ethernet phy
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Required properties:
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- compatible : Should contain phy id as "ethernet-phy-idAAAA.BBBB"
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The PHY device uses the binding described in
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Documentation/devicetree/bindings/net/phy.txt
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Optional properties:
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- vsc8531,vddmac : The vddmac in mV.
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- vsc8531,edge-slowdown : % the edge should be slowed down relative to
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the fastest possible edge time. Native sign
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need not enter.
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Edge rate sets the drive strength of the MAC
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interface output signals. Changing the drive
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strength will affect the edge rate of the output
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signal. The goal of this setting is to help
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reduce electrical emission (EMI) by being able
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to reprogram drive strength and in effect slow
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down the edge rate if desired. Table 1 shows the
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impact to the edge rate per VDDMAC supply for each
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drive strength setting.
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Ref: Table:1 - Edge rate change below.
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Note: see dt-bindings/net/mscc-phy-vsc8531.h for applicable values
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Table: 1 - Edge rate change
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----------------------------------------------------------------|
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| Edge Rate Change (VDDMAC) |
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| |
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| 3300 mV 2500 mV 1800 mV 1500 mV |
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|---------------------------------------------------------------|
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| Default Deafult Default Default |
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| (Fastest) (recommended) (recommended) |
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|---------------------------------------------------------------|
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| -2% -3% -5% -6% |
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|---------------------------------------------------------------|
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| -4% -6% -9% -14% |
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|---------------------------------------------------------------|
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| -7% -10% -16% -21% |
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|(recommended) (recommended) |
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|---------------------------------------------------------------|
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| -10% -14% -23% -29% |
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|---------------------------------------------------------------|
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| -17% -23% -35% -42% |
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|---------------------------------------------------------------|
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| -29% -37% -52% -58% |
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|---------------------------------------------------------------|
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| -53% -63% -76% -77% |
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| (slowest) |
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|---------------------------------------------------------------|
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Example:
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vsc8531_0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0007.0570";
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vsc8531,vddmac = <3300>;
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vsc8531,edge-slowdown = <21>;
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};
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@ -11,6 +11,8 @@
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#include <linux/mdio.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#include <dt-bindings/net/mscc-phy-vsc8531.h>
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enum rgmii_rx_clock_delay {
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RGMII_RX_CLK_DELAY_0_2_NS = 0,
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@ -37,6 +39,10 @@ enum rgmii_rx_clock_delay {
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#define MII_VSC85XX_INT_MASK_MASK 0xa000
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#define MII_VSC85XX_INT_STATUS 26
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define EDGE_RATE_CNTL_POS 5
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#define EDGE_RATE_CNTL_MASK 0x00E0
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#define MSCC_EXT_PAGE_ACCESS 31
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#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
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#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
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@ -50,6 +56,23 @@ enum rgmii_rx_clock_delay {
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#define PHY_ID_VSC8531 0x00070570
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#define PHY_ID_VSC8541 0x00070770
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struct edge_rate_table {
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u16 vddmac;
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int slowdown[MSCC_SLOWDOWN_MAX];
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};
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struct edge_rate_table edge_table[MSCC_VDDMAC_MAX] = {
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{3300, { 0, -2, -4, -7, -10, -17, -29, -53} },
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{2500, { 0, -3, -6, -10, -14, -23, -37, -63} },
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{1800, { 0, -5, -9, -16, -23, -35, -52, -76} },
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{1500, { 0, -6, -14, -21, -29, -42, -58, -77} },
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};
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struct vsc8531_private {
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u8 edge_slowdown;
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u16 vddmac;
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};
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static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
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{
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int rc;
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@ -58,6 +81,51 @@ static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
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return rc;
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}
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static u8 edge_rate_magic_get(u16 vddmac,
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int slowdown)
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{
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int rc = (MSCC_SLOWDOWN_MAX - 1);
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u8 vdd;
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u8 sd;
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for (vdd = 0; vdd < MSCC_VDDMAC_MAX; vdd++) {
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if (edge_table[vdd].vddmac == vddmac) {
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for (sd = 0; sd < MSCC_SLOWDOWN_MAX; sd++) {
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if (edge_table[vdd].slowdown[sd] <= slowdown) {
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rc = (MSCC_SLOWDOWN_MAX - sd - 1);
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break;
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}
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}
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}
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}
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return rc;
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}
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static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev,
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u8 edge_rate)
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{
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int rc;
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u16 reg_val;
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mutex_lock(&phydev->lock);
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
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if (rc != 0)
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goto out_unlock;
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reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
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reg_val &= ~(EDGE_RATE_CNTL_MASK);
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reg_val |= (edge_rate << EDGE_RATE_CNTL_POS);
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rc = phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
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if (rc != 0)
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goto out_unlock;
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rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
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out_unlock:
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mutex_unlock(&phydev->lock);
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return rc;
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}
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static int vsc85xx_mac_if_set(struct phy_device *phydev,
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phy_interface_t interface)
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{
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@ -116,9 +184,45 @@ static int vsc85xx_default_config(struct phy_device *phydev)
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return rc;
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}
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#ifdef CONFIG_OF_MDIO
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static int vsc8531_of_init(struct phy_device *phydev)
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{
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int rc;
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struct vsc8531_private *vsc8531 = phydev->priv;
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struct device *dev = &phydev->mdio.dev;
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struct device_node *of_node = dev->of_node;
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if (!of_node)
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return -ENODEV;
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rc = of_property_read_u16(of_node, "vsc8531,vddmac",
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&vsc8531->vddmac);
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if (rc == -EINVAL)
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vsc8531->vddmac = MSCC_VDDMAC_3300;
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rc = of_property_read_u8(of_node, "vsc8531,edge-slowdown",
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&vsc8531->edge_slowdown);
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if (rc == -EINVAL)
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vsc8531->edge_slowdown = 0;
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rc = 0;
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return rc;
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}
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#else
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static int vsc8531_of_init(struct phy_device *phydev)
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{
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return 0;
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}
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#endif /* CONFIG_OF_MDIO */
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static int vsc85xx_config_init(struct phy_device *phydev)
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{
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int rc;
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struct vsc8531_private *vsc8531 = phydev->priv;
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u8 edge_rate;
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rc = vsc8531_of_init(phydev);
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if (rc)
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return rc;
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rc = vsc85xx_default_config(phydev);
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if (rc)
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@ -128,6 +232,12 @@ static int vsc85xx_config_init(struct phy_device *phydev)
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if (rc)
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return rc;
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edge_rate = edge_rate_magic_get(vsc8531->vddmac,
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-(int)vsc8531->edge_slowdown);
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rc = vsc85xx_edge_rate_cntl_set(phydev, edge_rate);
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if (rc)
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return rc;
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rc = genphy_config_init(phydev);
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return rc;
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@ -160,6 +270,19 @@ static int vsc85xx_config_intr(struct phy_device *phydev)
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return rc;
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}
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static int vsc85xx_probe(struct phy_device *phydev)
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{
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struct vsc8531_private *vsc8531;
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vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
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if (!vsc8531)
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return -ENOMEM;
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phydev->priv = vsc8531;
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return 0;
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}
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/* Microsemi VSC85xx PHYs */
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static struct phy_driver vsc85xx_driver[] = {
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{
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@ -177,6 +300,7 @@ static struct phy_driver vsc85xx_driver[] = {
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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.probe = &vsc85xx_probe,
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},
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{
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.phy_id = PHY_ID_VSC8541,
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@ -193,6 +317,7 @@ static struct phy_driver vsc85xx_driver[] = {
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.config_intr = &vsc85xx_config_intr,
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.suspend = &genphy_suspend,
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.resume = &genphy_resume,
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.probe = &vsc85xx_probe,
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}
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};
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21
include/dt-bindings/net/mscc-phy-vsc8531.h
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21
include/dt-bindings/net/mscc-phy-vsc8531.h
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@ -0,0 +1,21 @@
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/*
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* Device Tree constants for Microsemi VSC8531 PHY
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*
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* Author: Nagaraju Lakkaraju
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*
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* License: Dual MIT/GPL
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* Copyright (c) 2016 Microsemi Corporation
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*/
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#ifndef _DT_BINDINGS_MSCC_VSC8531_H
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#define _DT_BINDINGS_MSCC_VSC8531_H
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/* MAC interface Edge rate control VDDMAC in milli Volts */
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#define MSCC_VDDMAC_3300 3300
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#define MSCC_VDDMAC_2500 2500
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#define MSCC_VDDMAC_1800 1800
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#define MSCC_VDDMAC_1500 1500
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#define MSCC_VDDMAC_MAX 4
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#define MSCC_SLOWDOWN_MAX 8
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#endif
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