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Merge branch 'Add-comphy-support-for-Armada-38x'

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Russell King says:

====================
Add comphy support for Armada 38x

This series adds support for the comphy for Armada 38x, which allows
these SoCs to use 2500BASE-X mode with appropriate SFP modules.

Tested on SolidRun Clearfog after updating for the 5.0 merge window
changes.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-02-07 18:10:26 -08:00
commit a4751093a2
8 changed files with 369 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
View File

@ -19,7 +19,7 @@ Optional properties:
"marvell,armada-370-neta" and 9800B for others.
- clock-names: List of names corresponding to clocks property; shall be
"core" for core clock and "bus" for the optional bus clock.
- phys: comphy for the ethernet port, see ../phy/phy-bindings.txt
Optional properties (valid only for Armada XP/38x):

40
Documentation/devicetree/bindings/phy/phy-armada38x-comphy.txt Normal file
View File

@ -0,0 +1,40 @@
mvebu armada 38x comphy driver
------------------------------
This comphy controller can be found on Marvell Armada 38x. It provides a
number of shared PHYs used by various interfaces (network, sata, usb,
PCIe...).
Required properties:
- compatible: should be "marvell,armada-380-comphy"
- reg: should contain the comphy register location and length.
- #address-cells: should be 1.
- #size-cells: should be 0.
A sub-node is required for each comphy lane provided by the comphy.
Required properties (child nodes):
- reg: comphy lane number.
- #phy-cells : from the generic phy bindings, must be 1. Defines the
input port to use for a given comphy lane.
Example:
comphy: phy@18300 {
compatible = "marvell,armada-380-comphy";
reg = <0x18300 0x100>;
#address-cells = <1>;
#size-cells = <0>;
cpm_comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cpm_comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
};

2
arch/arm/boot/dts/armada-388-clearfog.dtsi
View File

@ -93,6 +93,7 @@ &eth1 {
bm,pool-long = <2>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
phys = <&comphy1 1>;
phy-mode = "sgmii";
status = "okay";
};
@ -103,6 +104,7 @@ &eth2 {
bm,pool-short = <1>;
buffer-manager = <&bm>;
managed = "in-band-status";
phys = <&comphy5 2>;
phy-mode = "sgmii";
sfp = <&sfp>;
status = "okay";

37
arch/arm/boot/dts/armada-38x.dtsi
View File

@ -335,6 +335,43 @@ gateclk: clock-gating-control@18220 {
#clock-cells = <1>;
};
comphy: phy@18300 {
compatible = "marvell,armada-380-comphy";
reg = <0x18300 0x100>;
#address-cells = <1>;
#size-cells = <0>;
comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
comphy3: phy@3 {
reg = <3>;
#phy-cells = <1>;
};
comphy4: phy@4 {
reg = <4>;
#phy-cells = <1>;
};
comphy5: phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
coreclk: mvebu-sar@18600 {
compatible = "marvell,armada-380-core-clock";
reg = <0x18600 0x04>;

45
drivers/net/ethernet/marvell/mvneta.c
View File

@ -27,6 +27,7 @@
#include <linux/of_irq.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include <linux/phy/phy.h>
#include <linux/phy.h>
#include <linux/phylink.h>
#include <linux/platform_device.h>
@ -436,6 +437,7 @@ struct mvneta_port {
struct device_node *dn;
unsigned int tx_csum_limit;
struct phylink *phylink;
struct phy *comphy;
struct mvneta_bm *bm_priv;
struct mvneta_bm_pool *pool_long;
@ -3151,6 +3153,8 @@ static void mvneta_start_dev(struct mvneta_port *pp)
{
int cpu;
WARN_ON(phy_power_on(pp->comphy));
mvneta_max_rx_size_set(pp, pp->pkt_size);
mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
@ -3213,6 +3217,8 @@ static void mvneta_stop_dev(struct mvneta_port *pp)
mvneta_tx_reset(pp);
mvneta_rx_reset(pp);
WARN_ON(phy_power_off(pp->comphy));
}
static void mvneta_percpu_enable(void *arg)
@ -3338,6 +3344,7 @@ static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
struct phylink_link_state *state)
{
struct mvneta_port *pp = netdev_priv(ndev);
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
/* We only support QSGMII, SGMII, 802.3z and RGMII modes */
@ -3358,8 +3365,13 @@ static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
phylink_set(mask, Pause);
/* Half-duplex at speeds higher than 100Mbit is unsupported */
phylink_set(mask, 1000baseT_Full);
phylink_set(mask, 1000baseX_Full);
if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {
phylink_set(mask, 1000baseT_Full);
phylink_set(mask, 1000baseX_Full);
}
if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
phylink_set(mask, 2500baseX_Full);
}
if (!phy_interface_mode_is_8023z(state->interface)) {
/* 10M and 100M are only supported in non-802.3z mode */
@ -3373,6 +3385,11 @@ static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
__ETHTOOL_LINK_MODE_MASK_NBITS);
bitmap_and(state->advertising, state->advertising, mask,
__ETHTOOL_LINK_MODE_MASK_NBITS);
/* We can only operate at 2500BaseX or 1000BaseX. If requested
* to advertise both, only report advertising at 2500BaseX.
*/
phylink_helper_basex_speed(state);
}
static int mvneta_mac_link_state(struct net_device *ndev,
@ -3384,7 +3401,9 @@ static int mvneta_mac_link_state(struct net_device *ndev,
gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
if (gmac_stat & MVNETA_GMAC_SPEED_1000)
state->speed = SPEED_1000;
state->speed =
state->interface == PHY_INTERFACE_MODE_2500BASEX ?
SPEED_2500 : SPEED_1000;
else if (gmac_stat & MVNETA_GMAC_SPEED_100)
state->speed = SPEED_100;
else
@ -3499,12 +3518,20 @@ static void mvneta_mac_config(struct net_device *ndev, unsigned int mode,
MVNETA_GMAC_FORCE_LINK_DOWN);
}
/* When at 2.5G, the link partner can send frames with shortened
* preambles.
*/
if (state->speed == SPEED_2500)
new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
if (pp->comphy &&
(state->interface == PHY_INTERFACE_MODE_SGMII ||
state->interface == PHY_INTERFACE_MODE_1000BASEX ||
state->interface == PHY_INTERFACE_MODE_2500BASEX))
WARN_ON(phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
state->interface));
if (new_ctrl0 != gmac_ctrl0)
mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
if (new_ctrl2 != gmac_ctrl2)
@ -4404,7 +4431,7 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
phy_mode == PHY_INTERFACE_MODE_1000BASEX)
phy_interface_mode_is_8023z(phy_mode))
mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
else if (!phy_interface_mode_is_rgmii(phy_mode))
return -EINVAL;
@ -4421,6 +4448,7 @@ static int mvneta_probe(struct platform_device *pdev)
struct mvneta_port *pp;
struct net_device *dev;
struct phylink *phylink;
struct phy *comphy;
const char *dt_mac_addr;
char hw_mac_addr[ETH_ALEN];
const char *mac_from;
@ -4446,6 +4474,14 @@ static int mvneta_probe(struct platform_device *pdev)
goto err_free_irq;
}
comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
if (comphy == ERR_PTR(-EPROBE_DEFER)) {
err = -EPROBE_DEFER;
goto err_free_irq;
} else if (IS_ERR(comphy)) {
comphy = NULL;
}
phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode,
&mvneta_phylink_ops);
if (IS_ERR(phylink)) {
@ -4462,6 +4498,7 @@ static int mvneta_probe(struct platform_device *pdev)
pp = netdev_priv(dev);
spin_lock_init(&pp->lock);
pp->phylink = phylink;
pp->comphy = comphy;
pp->phy_interface = phy_mode;
pp->dn = dn;

10
drivers/phy/marvell/Kconfig
View File

@ -21,6 +21,16 @@ config PHY_BERLIN_USB
help
Enable this to support the USB PHY on Marvell Berlin SoCs.
config PHY_MVEBU_A38X_COMPHY
tristate "Marvell Armada 38x comphy driver"
depends on ARCH_MVEBU || COMPILE_TEST
depends on OF
select GENERIC_PHY
help
This driver allows to control the comphy, an hardware block providing
shared serdes PHYs on Marvell Armada 38x. Its serdes lanes can be
used by various controllers (Ethernet, sata, usb, PCIe...).
config PHY_MVEBU_CP110_COMPHY
tristate "Marvell CP110 comphy driver"
depends on ARCH_MVEBU || COMPILE_TEST

1
drivers/phy/marvell/Makefile
View File

@ -2,6 +2,7 @@
obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY) += phy-armada38x-comphy.o
obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o

237
drivers/phy/marvell/phy-armada38x-comphy.c Normal file
View File

@ -0,0 +1,237 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Russell King, Deep Blue Solutions Ltd.
*
* Partly derived from CP110 comphy driver by Antoine Tenart
* <antoine.tenart@bootlin.com>
*/
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/phy/phy.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#define MAX_A38X_COMPHY 6
#define MAX_A38X_PORTS 3
#define COMPHY_CFG1 0x00
#define COMPHY_CFG1_GEN_TX(x) ((x) << 26)
#define COMPHY_CFG1_GEN_TX_MSK COMPHY_CFG1_GEN_TX(15)
#define COMPHY_CFG1_GEN_RX(x) ((x) << 22)
#define COMPHY_CFG1_GEN_RX_MSK COMPHY_CFG1_GEN_RX(15)
#define GEN_SGMII_1_25GBPS 6
#define GEN_SGMII_3_125GBPS 8
#define COMPHY_STAT1 0x18
#define COMPHY_STAT1_PLL_RDY_TX BIT(3)
#define COMPHY_STAT1_PLL_RDY_RX BIT(2)
#define COMPHY_SELECTOR 0xfc
struct a38x_comphy;
struct a38x_comphy_lane {
void __iomem *base;
struct a38x_comphy *priv;
unsigned int n;
int port;
};
struct a38x_comphy {
void __iomem *base;
struct device *dev;
struct a38x_comphy_lane lane[MAX_A38X_COMPHY];
};
static const u8 gbe_mux[MAX_A38X_COMPHY][MAX_A38X_PORTS] = {
{ 0, 0, 0 },
{ 4, 5, 0 },
{ 0, 4, 0 },
{ 0, 0, 4 },
{ 0, 3, 0 },
{ 0, 0, 3 },
};
static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane,
unsigned int offset, u32 mask, u32 value)
{
u32 val;
val = readl_relaxed(lane->base + offset) & ~mask;
writel(val | value, lane->base + offset);
}
static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane,
unsigned int gen_tx, unsigned int gen_rx)
{
a38x_comphy_set_reg(lane, COMPHY_CFG1,
COMPHY_CFG1_GEN_TX_MSK | COMPHY_CFG1_GEN_RX_MSK,
COMPHY_CFG1_GEN_TX(gen_tx) |
COMPHY_CFG1_GEN_RX(gen_rx));
}
static int a38x_comphy_poll(struct a38x_comphy_lane *lane,
unsigned int offset, u32 mask, u32 value)
{
u32 val;
int ret;
ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val,
(val & mask) == value,
1000, 150000);
if (ret)
dev_err(lane->priv->dev,
"comphy%u: timed out waiting for status\n", lane->n);
return ret;
}
/*
* We only support changing the speed for comphys configured for GBE.
* Since that is all we do, we only poll for PLL ready status.
*/
static int a38x_comphy_set_mode(struct phy *phy, enum phy_mode mode, int sub)
{
struct a38x_comphy_lane *lane = phy_get_drvdata(phy);
unsigned int gen;
if (mode != PHY_MODE_ETHERNET)
return -EINVAL;
switch (sub) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
gen = GEN_SGMII_1_25GBPS;
break;
case PHY_INTERFACE_MODE_2500BASEX:
gen = GEN_SGMII_3_125GBPS;
break;
default:
return -EINVAL;
}
a38x_comphy_set_speed(lane, gen, gen);
return a38x_comphy_poll(lane, COMPHY_STAT1,
COMPHY_STAT1_PLL_RDY_TX |
COMPHY_STAT1_PLL_RDY_RX,
COMPHY_STAT1_PLL_RDY_TX |
COMPHY_STAT1_PLL_RDY_RX);
}
static const struct phy_ops a38x_comphy_ops = {
.set_mode = a38x_comphy_set_mode,
.owner = THIS_MODULE,
};
static struct phy *a38x_comphy_xlate(struct device *dev,
struct of_phandle_args *args)
{
struct a38x_comphy_lane *lane;
struct phy *phy;
u32 val;
if (WARN_ON(args->args[0] >= MAX_A38X_PORTS))
return ERR_PTR(-EINVAL);
phy = of_phy_simple_xlate(dev, args);
if (IS_ERR(phy))
return phy;
lane = phy_get_drvdata(phy);
if (lane->port >= 0)
return ERR_PTR(-EBUSY);
lane->port = args->args[0];
val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR);
val = (val >> (4 * lane->n)) & 0xf;
if (!gbe_mux[lane->n][lane->port] ||
val != gbe_mux[lane->n][lane->port]) {
dev_warn(lane->priv->dev,
"comphy%u: not configured for GBE\n", lane->n);
phy = ERR_PTR(-EINVAL);
}
return phy;
}
static int a38x_comphy_probe(struct platform_device *pdev)
{
struct phy_provider *provider;
struct device_node *child;
struct a38x_comphy *priv;
struct resource *res;
void __iomem *base;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
priv->dev = &pdev->dev;
priv->base = base;
for_each_available_child_of_node(pdev->dev.of_node, child) {
struct phy *phy;
int ret;
u32 val;
ret = of_property_read_u32(child, "reg", &val);
if (ret < 0) {
dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
ret);
continue;
}
if (val >= MAX_A38X_COMPHY || priv->lane[val].base) {
dev_err(&pdev->dev, "invalid 'reg' property\n");
continue;
}
phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops);
if (IS_ERR(phy))
return PTR_ERR(phy);
priv->lane[val].base = base + 0x28 * val;
priv->lane[val].priv = priv;
priv->lane[val].n = val;
priv->lane[val].port = -1;
phy_set_drvdata(phy, &priv->lane[val]);
}
dev_set_drvdata(&pdev->dev, priv);
provider = devm_of_phy_provider_register(&pdev->dev, a38x_comphy_xlate);
return PTR_ERR_OR_ZERO(provider);
}
static const struct of_device_id a38x_comphy_of_match_table[] = {
{ .compatible = "marvell,armada-380-comphy" },
{ },
};
MODULE_DEVICE_TABLE(of, a38x_comphy_of_match_table);
static struct platform_driver a38x_comphy_driver = {
.probe = a38x_comphy_probe,
.driver = {
.name = "armada-38x-comphy",
.of_match_table = a38x_comphy_of_match_table,
},
};
module_platform_driver(a38x_comphy_driver);
MODULE_AUTHOR("Russell King <rmk+kernel@armlinux.org.uk>");
MODULE_DESCRIPTION("Common PHY driver for Armada 38x SoCs");
MODULE_LICENSE("GPL v2");