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drm/amdgpu: add thick tile mode settings for Oland of gfx6
Adding thick tile mode for Oland to prevent UMD from getting mode value 0 Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Tested-by: Hui.Deng <hui.deng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -782,6 +782,25 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_1D_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16);
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tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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TILE_SPLIT(split_equal_to_row_size);
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tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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TILE_SPLIT(split_equal_to_row_size);
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tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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