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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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spi: McSPI off-mode support
Add context save/restore feature to McSPI driver. Signed-off-by: Hemanth V <hemanthv@ti.com> Reviewed-by: Aaro Koskinen <Aaro.Koskinen@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Hemanth V
Linus Torvalds
parent
0644c48672
commit
a41ae1ad90
@ -41,6 +41,9 @@
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#define OMAP2_MCSPI_MAX_FREQ 48000000
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/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
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#define OMAP2_MCSPI_MAX_CTRL 4
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#define OMAP2_MCSPI_REVISION 0x00
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#define OMAP2_MCSPI_SYSCONFIG 0x10
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#define OMAP2_MCSPI_SYSSTATUS 0x14
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@ -131,8 +134,21 @@ struct omap2_mcspi_cs {
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void __iomem *base;
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unsigned long phys;
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int word_len;
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/* Context save and restore shadow register */
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u32 chconf0;
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};
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/* used for context save and restore, structure members to be updated whenever
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* corresponding registers are modified.
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*/
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struct omap2_mcspi_regs {
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u32 sysconfig;
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u32 modulctrl;
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u32 wakeupenable;
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};
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static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
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static struct workqueue_struct *omap2_mcspi_wq;
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#define MOD_REG_BIT(val, mask, set) do { \
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@ -172,12 +188,27 @@ static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
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return __raw_readl(cs->base + idx);
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}
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static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
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{
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struct omap2_mcspi_cs *cs = spi->controller_state;
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return cs->chconf0;
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}
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static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
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{
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struct omap2_mcspi_cs *cs = spi->controller_state;
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cs->chconf0 = val;
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
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}
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static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
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int is_read, int enable)
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{
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u32 l, rw;
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l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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l = mcspi_cached_chconf0(spi);
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if (is_read) /* 1 is read, 0 write */
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rw = OMAP2_MCSPI_CHCONF_DMAR;
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@ -185,7 +216,7 @@ static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
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rw = OMAP2_MCSPI_CHCONF_DMAW;
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MOD_REG_BIT(l, rw, enable);
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
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mcspi_write_chconf0(spi, l);
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}
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static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
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@ -200,9 +231,9 @@ static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
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{
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u32 l;
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l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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l = mcspi_cached_chconf0(spi);
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MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
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mcspi_write_chconf0(spi, l);
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}
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static void omap2_mcspi_set_master_mode(struct spi_master *master)
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@ -217,6 +248,41 @@ static void omap2_mcspi_set_master_mode(struct spi_master *master)
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MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
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MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
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mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
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omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
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}
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static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
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{
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struct spi_master *spi_cntrl;
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spi_cntrl = mcspi->master;
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/* McSPI: context restore */
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mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
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omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
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mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
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omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
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mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
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omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
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}
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static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
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{
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clk_disable(mcspi->ick);
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clk_disable(mcspi->fck);
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}
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static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
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{
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if (clk_enable(mcspi->ick))
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return -ENODEV;
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if (clk_enable(mcspi->fck))
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return -ENODEV;
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omap2_mcspi_restore_ctx(mcspi);
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return 0;
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}
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static unsigned
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@ -357,7 +423,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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c = count;
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word_len = cs->word_len;
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l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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l = mcspi_cached_chconf0(spi);
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l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
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/* We store the pre-calculated register addresses on stack to speed
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@ -397,8 +463,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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* more word i/o: switch to rx+tx
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*/
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if (c == 0 && tx == NULL)
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mcspi_write_cs_reg(spi,
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OMAP2_MCSPI_CHCONF0, l);
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mcspi_write_chconf0(spi, l);
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %02x\n",
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@ -436,8 +501,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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* more word i/o: switch to rx+tx
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*/
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if (c == 0 && tx == NULL)
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mcspi_write_cs_reg(spi,
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OMAP2_MCSPI_CHCONF0, l);
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mcspi_write_chconf0(spi, l);
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %04x\n",
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@ -475,8 +539,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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* more word i/o: switch to rx+tx
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*/
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if (c == 0 && tx == NULL)
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mcspi_write_cs_reg(spi,
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OMAP2_MCSPI_CHCONF0, l);
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mcspi_write_chconf0(spi, l);
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %04x\n",
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@ -505,10 +568,12 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
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{
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struct omap2_mcspi_cs *cs = spi->controller_state;
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struct omap2_mcspi *mcspi;
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struct spi_master *spi_cntrl;
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u32 l = 0, div = 0;
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u8 word_len = spi->bits_per_word;
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mcspi = spi_master_get_devdata(spi->master);
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spi_cntrl = mcspi->master;
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if (t != NULL && t->bits_per_word)
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word_len = t->bits_per_word;
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@ -522,7 +587,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
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} else
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div = 15;
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l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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l = mcspi_cached_chconf0(spi);
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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* REVISIT: this controller could support SPI_3WIRE mode.
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@ -554,7 +619,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
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else
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l &= ~OMAP2_MCSPI_CHCONF_PHA;
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
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mcspi_write_chconf0(spi, l);
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dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
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OMAP2_MCSPI_MAX_FREQ / (1 << div),
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@ -647,6 +712,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
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return -ENOMEM;
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cs->base = mcspi->base + spi->chip_select * 0x14;
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cs->phys = mcspi->phys + spi->chip_select * 0x14;
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cs->chconf0 = 0;
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spi->controller_state = cs;
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}
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@ -657,11 +723,11 @@ static int omap2_mcspi_setup(struct spi_device *spi)
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return ret;
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}
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clk_enable(mcspi->ick);
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clk_enable(mcspi->fck);
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if (omap2_mcspi_enable_clocks(mcspi))
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return -ENODEV;
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ret = omap2_mcspi_setup_transfer(spi, NULL);
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clk_disable(mcspi->fck);
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clk_disable(mcspi->ick);
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omap2_mcspi_disable_clocks(mcspi);
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return ret;
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}
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@ -693,8 +759,8 @@ static void omap2_mcspi_work(struct work_struct *work)
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mcspi = container_of(work, struct omap2_mcspi, work);
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spin_lock_irq(&mcspi->lock);
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clk_enable(mcspi->ick);
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clk_enable(mcspi->fck);
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if (omap2_mcspi_enable_clocks(mcspi))
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goto out;
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/* We only enable one channel at a time -- the one whose message is
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* at the head of the queue -- although this controller would gladly
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@ -741,13 +807,13 @@ static void omap2_mcspi_work(struct work_struct *work)
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cs_active = 1;
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}
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chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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chconf = mcspi_cached_chconf0(spi);
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chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
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if (t->tx_buf == NULL)
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chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
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else if (t->rx_buf == NULL)
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chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf);
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mcspi_write_chconf0(spi, chconf);
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if (t->len) {
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unsigned count;
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@ -796,9 +862,9 @@ static void omap2_mcspi_work(struct work_struct *work)
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spin_lock_irq(&mcspi->lock);
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}
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clk_disable(mcspi->fck);
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clk_disable(mcspi->ick);
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omap2_mcspi_disable_clocks(mcspi);
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out:
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spin_unlock_irq(&mcspi->lock);
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}
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@ -885,8 +951,8 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
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struct spi_master *master = mcspi->master;
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u32 tmp;
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clk_enable(mcspi->ick);
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clk_enable(mcspi->fck);
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if (omap2_mcspi_enable_clocks(mcspi))
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return -1;
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mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
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OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
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@ -894,18 +960,18 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
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tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
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} while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
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mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
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OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
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OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
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OMAP2_MCSPI_SYSCONFIG_SMARTIDLE);
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tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
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OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
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OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
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mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
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omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
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mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
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OMAP2_MCSPI_WAKEUPENABLE_WKEN);
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tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
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mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
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omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
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omap2_mcspi_set_master_mode(master);
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clk_disable(mcspi->fck);
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clk_disable(mcspi->ick);
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omap2_mcspi_disable_clocks(mcspi);
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return 0;
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}
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