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drm/i915/bxt: IPC WA for Broxton

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Display Workarounds #1135
If IPC is enabled in BXT, display underruns are observed.
WA: The Line Time programmed in the WM_LINETIME register should be
half of the actual calculated Line Time.

Programmed Line Time = 1/2*Calculated Line Time

Changes since V1:
 - Add Workaround number in commit & code
Changes since V2 (from Paulo):
 - Bikeshed white space and make the WA tag look like the others

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161201154940.24446-3-mahesh1.kumar@intel.com
This commit is contained in:
Mahesh Kumar 2016-12-01 21:19:34 +05:30 committed by Paulo Zanoni
parent ef8a4fb479
commit a3a8986cb2
3 changed files with 15 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/i915_drv.c
View File

@ -1239,6 +1239,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
intel_runtime_pm_enable(dev_priv); intel_runtime_pm_enable(dev_priv);
dev_priv->ipc_enabled = false;
/* Everything is in place, we can now relax! */ /* Everything is in place, we can now relax! */
DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
driver.name, driver.major, driver.minor, driver.patchlevel, driver.name, driver.major, driver.minor, driver.patchlevel,

2
drivers/gpu/drm/i915/i915_drv.h
View File

@ -2329,6 +2329,8 @@ struct drm_i915_private {
/* perform PHY state sanity checks? */ /* perform PHY state sanity checks? */
bool chv_phy_assert[2]; bool chv_phy_assert[2];
bool ipc_enabled;
/* Used to save the pipe-to-encoder mapping for audio */ /* Used to save the pipe-to-encoder mapping for audio */
struct intel_encoder *av_enc_map[I915_MAX_PIPES]; struct intel_encoder *av_enc_map[I915_MAX_PIPES];

13
drivers/gpu/drm/i915/intel_pm.c
View File

@ -3761,7 +3761,10 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
static uint32_t static uint32_t
skl_compute_linetime_wm(struct intel_crtc_state *cstate) skl_compute_linetime_wm(struct intel_crtc_state *cstate)
{ {
struct drm_atomic_state *state = cstate->base.state;
struct drm_i915_private *dev_priv = to_i915(state->dev);
uint32_t pixel_rate; uint32_t pixel_rate;
uint32_t linetime_wm;
if (!cstate->base.active) if (!cstate->base.active)
return 0; return 0;
@ -3771,8 +3774,14 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
if (WARN_ON(pixel_rate == 0)) if (WARN_ON(pixel_rate == 0))
return 0; return 0;
return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000, linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
pixel_rate); 1000, pixel_rate);
/* Display WA #1135: bxt. */
if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
return linetime_wm;
} }
static void skl_compute_transition_wm(struct intel_crtc_state *cstate, static void skl_compute_transition_wm(struct intel_crtc_state *cstate,