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perf_counter/x86: Remove the IRQ (non-NMI) handling bits
Remove the IRQ (non-NMI) handling bits as NMI will be used always. Signed-off-by: Yong Wang <yong.y.wang@intel.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: John Kacur <jkacur@redhat.com> LKML-Reference: <20090603051255.GA2791@ywang-moblin2.bj.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -49,7 +49,6 @@ BUILD_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
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BUILD_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
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#ifdef CONFIG_PERF_COUNTERS
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BUILD_INTERRUPT(perf_counter_interrupt, LOCAL_PERF_VECTOR)
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BUILD_INTERRUPT(perf_pending_interrupt, LOCAL_PENDING_VECTOR)
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#endif
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@ -29,7 +29,6 @@
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extern void apic_timer_interrupt(void);
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extern void generic_interrupt(void);
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extern void error_interrupt(void);
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extern void perf_counter_interrupt(void);
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extern void perf_pending_interrupt(void);
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extern void spurious_interrupt(void);
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@ -106,11 +106,6 @@
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*/
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#define LOCAL_TIMER_VECTOR 0xef
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/*
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* Performance monitoring interrupt vector:
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*/
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#define LOCAL_PERF_VECTOR 0xee
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/*
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* Generic system vector for platform specific use
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*/
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@ -40,7 +40,7 @@ struct cpu_hw_counters {
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struct x86_pmu {
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const char *name;
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int version;
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int (*handle_irq)(struct pt_regs *, int);
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int (*handle_irq)(struct pt_regs *);
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void (*disable_all)(void);
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void (*enable_all)(void);
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void (*enable)(struct hw_perf_counter *, int);
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@ -755,7 +755,7 @@ static void intel_pmu_reset(void)
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* This handler is triggered by the local APIC, so the APIC IRQ handling
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* rules apply:
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*/
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static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
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static int intel_pmu_handle_irq(struct pt_regs *regs)
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{
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struct cpu_hw_counters *cpuc;
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struct cpu_hw_counters;
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@ -794,7 +794,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
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if (!intel_pmu_save_and_restart(counter))
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continue;
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if (perf_counter_overflow(counter, nmi, regs, 0))
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if (perf_counter_overflow(counter, 1, regs, 0))
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intel_pmu_disable_counter(&counter->hw, bit);
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}
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@ -812,7 +812,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
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return 1;
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}
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static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
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static int amd_pmu_handle_irq(struct pt_regs *regs)
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{
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int cpu, idx, handled = 0;
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struct cpu_hw_counters *cpuc;
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@ -840,22 +840,13 @@ static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
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if (!x86_perf_counter_set_period(counter, hwc, idx))
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continue;
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if (perf_counter_overflow(counter, nmi, regs, 0))
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if (perf_counter_overflow(counter, 1, regs, 0))
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amd_pmu_disable_counter(hwc, idx);
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}
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return handled;
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}
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void smp_perf_counter_interrupt(struct pt_regs *regs)
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{
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irq_enter();
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apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
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ack_APIC_irq();
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x86_pmu.handle_irq(regs, 0);
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irq_exit();
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}
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void smp_perf_pending_interrupt(struct pt_regs *regs)
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{
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irq_enter();
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@ -910,7 +901,7 @@ perf_counter_nmi_handler(struct notifier_block *self,
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* If the first NMI handles both, the latter will be empty and daze
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* the CPU.
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*/
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x86_pmu.handle_irq(regs, 1);
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x86_pmu.handle_irq(regs);
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return NOTIFY_STOP;
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}
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@ -1026,8 +1026,6 @@ apicinterrupt SPURIOUS_APIC_VECTOR \
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spurious_interrupt smp_spurious_interrupt
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#ifdef CONFIG_PERF_COUNTERS
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apicinterrupt LOCAL_PERF_VECTOR \
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perf_counter_interrupt smp_perf_counter_interrupt
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apicinterrupt LOCAL_PENDING_VECTOR \
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perf_pending_interrupt smp_perf_pending_interrupt
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#endif
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@ -165,7 +165,6 @@ static void __init apic_intr_init(void)
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alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
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alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
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# ifdef CONFIG_PERF_COUNTERS
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alloc_intr_gate(LOCAL_PERF_VECTOR, perf_counter_interrupt);
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alloc_intr_gate(LOCAL_PENDING_VECTOR, perf_pending_interrupt);
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# endif
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@ -155,7 +155,6 @@ static void __init apic_intr_init(void)
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/* Performance monitoring interrupt: */
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#ifdef CONFIG_PERF_COUNTERS
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alloc_intr_gate(LOCAL_PERF_VECTOR, perf_counter_interrupt);
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alloc_intr_gate(LOCAL_PENDING_VECTOR, perf_pending_interrupt);
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#endif
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}
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