mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ASoC: Add max98926 codec driver
Signed-off-by: anish kumar <yesanishhere@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
anish kumar
Mark Brown
parent
92e963f50f
commit
a2e2876aa0
32
Documentation/devicetree/bindings/sound/max98926.txt
Normal file
32
Documentation/devicetree/bindings/sound/max98926.txt
Normal file
@ -0,0 +1,32 @@
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max98926 audio CODEC
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This device supports I2C.
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Required properties:
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- compatible : "maxim,max98926"
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- vmon-slot-no : slot number used to send voltage information
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or in inteleave mode this will be used as
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interleave slot.
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- imon-slot-no : slot number used to send current information
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- interleave-mode : When using two MAX98926 in a system it is
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possible to create ADC data that that will
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overflow the frame size. Digital Audio Interleave
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mode provides a means to output VMON and IMON data
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from two devices on a single DOUT line when running
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smaller frames sizes such as 32 BCLKS per LRCLK or
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48 BCLKS per LRCLK.
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- reg : the I2C address of the device for I2C
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Example:
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codec: max98926@1a {
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compatible = "maxim,max98926";
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vmon-slot-no = <0>;
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imon-slot-no = <2>;
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reg = <0x1a>;
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};
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@ -80,6 +80,7 @@ config SND_SOC_ALL_CODECS
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select SND_SOC_MAX98095 if I2C
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select SND_SOC_MAX98357A if GPIOLIB
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select SND_SOC_MAX98925 if I2C
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select SND_SOC_MAX98926 if I2C
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select SND_SOC_MAX9850 if I2C
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select SND_SOC_MAX9768 if I2C
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select SND_SOC_MAX9877 if I2C
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@ -519,6 +520,9 @@ config SND_SOC_MAX98357A
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config SND_SOC_MAX98925
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tristate
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config SND_SOC_MAX98926
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tristate
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config SND_SOC_MAX9850
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tristate
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@ -75,6 +75,7 @@ snd-soc-max98090-objs := max98090.o
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snd-soc-max98095-objs := max98095.o
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snd-soc-max98357a-objs := max98357a.o
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snd-soc-max98925-objs := max98925.o
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snd-soc-max98926-objs := max98926.o
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snd-soc-max9850-objs := max9850.o
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snd-soc-mc13783-objs := mc13783.o
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snd-soc-ml26124-objs := ml26124.o
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@ -279,6 +280,7 @@ obj-$(CONFIG_SND_SOC_MAX98090) += snd-soc-max98090.o
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obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o
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obj-$(CONFIG_SND_SOC_MAX98357A) += snd-soc-max98357a.o
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obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o
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obj-$(CONFIG_SND_SOC_MAX98926) += snd-soc-max98926.o
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obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
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obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
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obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o
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604
sound/soc/codecs/max98926.c
Normal file
604
sound/soc/codecs/max98926.c
Normal file
@ -0,0 +1,604 @@
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/*
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* max98926.c -- ALSA SoC MAX98926 driver
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* Copyright 2013-15 Maxim Integrated Products
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/cdev.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/tlv.h>
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#include "max98926.h"
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static const char * const max98926_boost_voltage_txt[] = {
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"8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
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"6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
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};
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static const char * const max98926_boost_current_txt[] = {
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"0.6", "0.8", "1.0", "1.2", "1.4", "1.6", "1.8", "2.0",
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"2.2", "2.4", "2.6", "2.8", "3.2", "3.6", "4.0", "4.4"
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};
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static const char *const max98926_dai_txt[] = {
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"Left", "Right", "LeftRight", "LeftRightDiv2",
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};
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static const char *const max98926_pdm_ch_text[] = {
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"Current", "Voltage",
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};
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static const char *const max98926_hpf_cutoff_txt[] = {
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"Disable", "DC Block", "100Hz",
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"200Hz", "400Hz", "800Hz",
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};
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static struct reg_default max98926_reg[] = {
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{ 0x0B, 0x00 }, /* IRQ Enable0 */
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{ 0x0C, 0x00 }, /* IRQ Enable1 */
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{ 0x0D, 0x00 }, /* IRQ Enable2 */
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{ 0x0E, 0x00 }, /* IRQ Clear0 */
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{ 0x0F, 0x00 }, /* IRQ Clear1 */
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{ 0x10, 0x00 }, /* IRQ Clear2 */
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{ 0x11, 0xC0 }, /* Map0 */
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{ 0x12, 0x00 }, /* Map1 */
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{ 0x13, 0x00 }, /* Map2 */
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{ 0x14, 0xF0 }, /* Map3 */
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{ 0x15, 0x00 }, /* Map4 */
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{ 0x16, 0xAB }, /* Map5 */
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{ 0x17, 0x89 }, /* Map6 */
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{ 0x18, 0x00 }, /* Map7 */
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{ 0x19, 0x00 }, /* Map8 */
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{ 0x1A, 0x04 }, /* DAI Clock Mode 1 */
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{ 0x1B, 0x00 }, /* DAI Clock Mode 2 */
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{ 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
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{ 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
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{ 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
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{ 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
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{ 0x20, 0x50 }, /* Format */
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{ 0x21, 0x00 }, /* TDM Slot Select */
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{ 0x22, 0x00 }, /* DOUT Configuration VMON */
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{ 0x23, 0x00 }, /* DOUT Configuration IMON */
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{ 0x24, 0x00 }, /* DOUT Configuration VBAT */
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{ 0x25, 0x00 }, /* DOUT Configuration VBST */
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{ 0x26, 0x00 }, /* DOUT Configuration FLAG */
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{ 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
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{ 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
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{ 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
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{ 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
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{ 0x2B, 0x02 }, /* DOUT Drive Strength */
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{ 0x2C, 0x90 }, /* Filters */
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{ 0x2D, 0x00 }, /* Gain */
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{ 0x2E, 0x02 }, /* Gain Ramping */
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{ 0x2F, 0x00 }, /* Speaker Amplifier */
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{ 0x30, 0x0A }, /* Threshold */
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{ 0x31, 0x00 }, /* ALC Attack */
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{ 0x32, 0x80 }, /* ALC Atten and Release */
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{ 0x33, 0x00 }, /* ALC Infinite Hold Release */
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{ 0x34, 0x92 }, /* ALC Configuration */
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{ 0x35, 0x01 }, /* Boost Converter */
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{ 0x36, 0x00 }, /* Block Enable */
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{ 0x37, 0x00 }, /* Configuration */
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{ 0x38, 0x00 }, /* Global Enable */
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{ 0x3A, 0x00 }, /* Boost Limiter */
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};
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static const struct soc_enum max98926_voltage_enum[] = {
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SOC_ENUM_SINGLE(MAX98926_DAI_CLK_DIV_N_LSBS, 0,
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ARRAY_SIZE(max98926_pdm_ch_text),
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max98926_pdm_ch_text),
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};
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static const struct snd_kcontrol_new max98926_voltage_control =
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SOC_DAPM_ENUM("Route", max98926_voltage_enum);
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static const struct soc_enum max98926_current_enum[] = {
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SOC_ENUM_SINGLE(MAX98926_DAI_CLK_DIV_N_LSBS,
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MAX98926_PDM_SOURCE_1_SHIFT,
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ARRAY_SIZE(max98926_pdm_ch_text),
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max98926_pdm_ch_text),
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};
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static const struct snd_kcontrol_new max98926_current_control =
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SOC_DAPM_ENUM("Route", max98926_current_enum);
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static const struct snd_kcontrol_new max98926_mixer_controls[] = {
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SOC_DAPM_SINGLE("PCM Single Switch", MAX98926_SPK_AMP,
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MAX98926_INSELECT_MODE_SHIFT, 0, 0),
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SOC_DAPM_SINGLE("PDM Single Switch", MAX98926_SPK_AMP,
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MAX98926_INSELECT_MODE_SHIFT, 1, 0),
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};
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static const struct snd_kcontrol_new max98926_dai_controls[] = {
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SOC_DAPM_SINGLE("Left", MAX98926_GAIN,
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MAX98926_DAC_IN_SEL_SHIFT, 0, 0),
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SOC_DAPM_SINGLE("Right", MAX98926_GAIN,
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MAX98926_DAC_IN_SEL_SHIFT, 1, 0),
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SOC_DAPM_SINGLE("LeftRight", MAX98926_GAIN,
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MAX98926_DAC_IN_SEL_SHIFT, 2, 0),
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SOC_DAPM_SINGLE("(Left+Right)/2 Switch", MAX98926_GAIN,
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MAX98926_DAC_IN_SEL_SHIFT, 3, 0),
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};
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static const struct snd_soc_dapm_widget max98926_dapm_widgets[] = {
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SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0,
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SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_DAC("Amp Enable", NULL, MAX98926_BLOCK_ENABLE,
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MAX98926_SPK_EN_SHIFT, 0),
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SND_SOC_DAPM_SUPPLY("Global Enable", MAX98926_GLOBAL_ENABLE,
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MAX98926_EN_SHIFT, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("VI Enable", MAX98926_BLOCK_ENABLE,
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MAX98926_ADC_IMON_EN_WIDTH |
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MAX98926_ADC_VMON_EN_SHIFT,
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0, NULL, 0),
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SND_SOC_DAPM_PGA("BST Enable", MAX98926_BLOCK_ENABLE,
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MAX98926_BST_EN_SHIFT, 0, NULL, 0),
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SND_SOC_DAPM_OUTPUT("BE_OUT"),
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SND_SOC_DAPM_MIXER("PCM Sel", MAX98926_SPK_AMP,
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MAX98926_INSELECT_MODE_SHIFT, 0,
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&max98926_mixer_controls[0],
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ARRAY_SIZE(max98926_mixer_controls)),
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SND_SOC_DAPM_MIXER("DAI Sel",
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MAX98926_GAIN, MAX98926_DAC_IN_SEL_SHIFT, 0,
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&max98926_dai_controls[0],
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ARRAY_SIZE(max98926_dai_controls)),
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SND_SOC_DAPM_MUX("PDM CH1 Source",
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MAX98926_DAI_CLK_DIV_N_LSBS,
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MAX98926_PDM_CURRENT_SHIFT,
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0, &max98926_current_control),
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SND_SOC_DAPM_MUX("PDM CH0 Source",
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MAX98926_DAI_CLK_DIV_N_LSBS,
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MAX98926_PDM_VOLTAGE_SHIFT,
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0, &max98926_voltage_control),
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};
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static const struct snd_soc_dapm_route max98926_audio_map[] = {
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{"VI Enable", NULL, "DAI_OUT"},
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{"DAI Sel", "Left", "VI Enable"},
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{"DAI Sel", "Right", "VI Enable"},
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{"DAI Sel", "LeftRight", "VI Enable"},
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{"DAI Sel", "LeftRightDiv2", "VI Enable"},
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{"PCM Sel", "PCM", "DAI Sel"},
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{"PDM CH1 Source", "Current", "DAI_OUT"},
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{"PDM CH1 Source", "Voltage", "DAI_OUT"},
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{"PDM CH0 Source", "Current", "DAI_OUT"},
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{"PDM CH0 Source", "Voltage", "DAI_OUT"},
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{"PCM Sel", "Analog", "PDM CH1 Source"},
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{"PCM Sel", "Analog", "PDM CH0 Source"},
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{"Amp Enable", NULL, "PCM Sel"},
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{"BST Enable", NULL, "Amp Enable"},
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{"BE_OUT", NULL, "BST Enable"},
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};
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static bool max98926_volatile_register(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case MAX98926_VBAT_DATA:
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case MAX98926_VBST_DATA:
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case MAX98926_LIVE_STATUS0:
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case MAX98926_LIVE_STATUS1:
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case MAX98926_LIVE_STATUS2:
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case MAX98926_STATE0:
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case MAX98926_STATE1:
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case MAX98926_STATE2:
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case MAX98926_FLAG0:
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case MAX98926_FLAG1:
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case MAX98926_FLAG2:
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case MAX98926_VERSION:
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return true;
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default:
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return false;
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}
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}
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static bool max98926_readable_register(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case MAX98926_IRQ_CLEAR0:
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case MAX98926_IRQ_CLEAR1:
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case MAX98926_IRQ_CLEAR2:
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case MAX98926_ALC_HOLD_RLS:
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return false;
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default:
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return true;
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}
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};
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DECLARE_TLV_DB_SCALE(max98926_spk_tlv, -600, 100, 0);
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DECLARE_TLV_DB_RANGE(max98926_current_tlv,
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0, 11, TLV_DB_SCALE_ITEM(20, 20, 0),
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12, 15, TLV_DB_SCALE_ITEM(320, 40, 0),
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);
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static SOC_ENUM_SINGLE_DECL(max98926_dac_hpf_cutoff,
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MAX98926_FILTERS, MAX98926_DAC_HPF_SHIFT,
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max98926_hpf_cutoff_txt);
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static SOC_ENUM_SINGLE_DECL(max98926_boost_voltage,
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MAX98926_CONFIGURATION, MAX98926_BST_VOUT_SHIFT,
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max98926_boost_voltage_txt);
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static const struct snd_kcontrol_new max98926_snd_controls[] = {
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SOC_SINGLE_TLV("Speaker Volume", MAX98926_GAIN,
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MAX98926_SPK_GAIN_SHIFT,
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(1<<MAX98926_SPK_GAIN_WIDTH)-1, 0,
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max98926_spk_tlv),
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SOC_SINGLE("Ramp Switch", MAX98926_GAIN_RAMPING,
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MAX98926_SPK_RMP_EN_SHIFT, 1, 0),
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SOC_SINGLE("ZCD Switch", MAX98926_GAIN_RAMPING,
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MAX98926_SPK_ZCD_EN_SHIFT, 1, 0),
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SOC_SINGLE("ALC Switch", MAX98926_THRESHOLD,
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MAX98926_ALC_EN_SHIFT, 1, 0),
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SOC_SINGLE("ALC Threshold", MAX98926_THRESHOLD,
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MAX98926_ALC_TH_SHIFT,
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(1<<MAX98926_ALC_TH_WIDTH)-1, 0),
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SOC_ENUM("Boost Output Voltage", max98926_boost_voltage),
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SOC_SINGLE_TLV("Boost Current Limit", MAX98926_BOOST_LIMITER,
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MAX98926_BST_ILIM_SHIFT,
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(1<<MAX98926_BST_ILIM_SHIFT)-1, 0,
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max98926_current_tlv),
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SOC_ENUM("DAC HPF Cutoff", max98926_dac_hpf_cutoff),
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SOC_DOUBLE("PDM Channel One", MAX98926_DAI_CLK_DIV_N_LSBS,
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MAX98926_PDM_CHANNEL_1_SHIFT,
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MAX98926_PDM_CHANNEL_1_HIZ, 1, 0),
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SOC_DOUBLE("PDM Channel Zero", MAX98926_DAI_CLK_DIV_N_LSBS,
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MAX98926_PDM_CHANNEL_0_SHIFT,
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MAX98926_PDM_CHANNEL_0_HIZ, 1, 0),
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};
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static const struct {
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int rate;
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int sr;
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} rate_table[] = {
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{
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.rate = 8000,
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.sr = 0,
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},
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{
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.rate = 11025,
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.sr = 1,
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},
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{
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.rate = 12000,
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.sr = 2,
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},
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{
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.rate = 16000,
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.sr = 3,
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},
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{
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.rate = 22050,
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.sr = 4,
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},
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{
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.rate = 24000,
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.sr = 5,
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},
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{
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.rate = 32000,
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.sr = 6,
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},
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{
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.rate = 44100,
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.sr = 7,
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},
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{
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.rate = 48000,
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.sr = 8,
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},
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};
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static void max98926_set_sense_data(struct max98926_priv *max98926)
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{
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regmap_update_bits(max98926->regmap,
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MAX98926_DOUT_CFG_VMON,
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MAX98926_DAI_VMON_EN_MASK,
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MAX98926_DAI_VMON_EN_MASK);
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regmap_update_bits(max98926->regmap,
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MAX98926_DOUT_CFG_IMON,
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MAX98926_DAI_IMON_EN_MASK,
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MAX98926_DAI_IMON_EN_MASK);
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if (!max98926->interleave_mode) {
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/* set VMON slots */
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regmap_update_bits(max98926->regmap,
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MAX98926_DOUT_CFG_VMON,
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MAX98926_DAI_VMON_SLOT_MASK,
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max98926->v_slot);
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/* set IMON slots */
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regmap_update_bits(max98926->regmap,
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MAX98926_DOUT_CFG_IMON,
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MAX98926_DAI_IMON_SLOT_MASK,
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max98926->i_slot);
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} else {
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/* enable interleave mode */
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regmap_update_bits(max98926->regmap,
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MAX98926_FORMAT,
|
||||
MAX98926_DAI_INTERLEAVE_MASK,
|
||||
MAX98926_DAI_INTERLEAVE_MASK);
|
||||
/* set interleave slots */
|
||||
regmap_update_bits(max98926->regmap,
|
||||
MAX98926_DOUT_CFG_VBAT,
|
||||
MAX98926_DAI_INTERLEAVE_SLOT_MASK,
|
||||
max98926->v_slot);
|
||||
}
|
||||
}
|
||||
|
||||
static int max98926_dai_set_fmt(struct snd_soc_dai *codec_dai,
|
||||
unsigned int fmt)
|
||||
{
|
||||
struct snd_soc_codec *codec = codec_dai->codec;
|
||||
struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
|
||||
unsigned int invert = 0;
|
||||
|
||||
dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
||||
case SND_SOC_DAIFMT_CBS_CFS:
|
||||
max98926_set_sense_data(max98926);
|
||||
break;
|
||||
default:
|
||||
dev_err(codec->dev, "DAI clock mode unsupported");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
||||
case SND_SOC_DAIFMT_NB_NF:
|
||||
break;
|
||||
case SND_SOC_DAIFMT_NB_IF:
|
||||
invert = MAX98926_DAI_WCI_MASK;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_IB_NF:
|
||||
invert = MAX98926_DAI_BCI_MASK;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_IB_IF:
|
||||
invert = MAX98926_DAI_BCI_MASK | MAX98926_DAI_WCI_MASK;
|
||||
break;
|
||||
default:
|
||||
dev_err(codec->dev, "DAI invert mode unsupported");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_write(max98926->regmap,
|
||||
MAX98926_FORMAT, MAX98926_DAI_DLY_MASK);
|
||||
regmap_update_bits(max98926->regmap, MAX98926_FORMAT,
|
||||
MAX98926_DAI_BCI_MASK, invert);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int max98926_dai_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
int dai_sr = -EINVAL;
|
||||
int rate = params_rate(params), i;
|
||||
struct snd_soc_codec *codec = dai->codec;
|
||||
struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
|
||||
/* BCLK/LRCLK ratio calculation */
|
||||
int blr_clk_ratio = params_channels(params) * max98926->ch_size;
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
regmap_update_bits(max98926->regmap,
|
||||
MAX98926_FORMAT,
|
||||
MAX98926_DAI_CHANSZ_MASK,
|
||||
MAX98926_DAI_CHANSZ_16);
|
||||
max98926->ch_size = 16;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
regmap_update_bits(max98926->regmap,
|
||||
MAX98926_FORMAT,
|
||||
MAX98926_DAI_CHANSZ_MASK,
|
||||
MAX98926_DAI_CHANSZ_24);
|
||||
max98926->ch_size = 24;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
regmap_update_bits(max98926->regmap,
|
||||
MAX98926_FORMAT,
|
||||
MAX98926_DAI_CHANSZ_MASK,
|
||||
MAX98926_DAI_CHANSZ_32);
|
||||
max98926->ch_size = 32;
|
||||
break;
|
||||
default:
|
||||
dev_dbg(codec->dev, "format unsupported %d",
|
||||
params_format(params));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (blr_clk_ratio) {
|
||||
case 32:
|
||||
regmap_update_bits(max98926->regmap,
|
||||
MAX98926_DAI_CLK_MODE2,
|
||||
MAX98926_DAI_BSEL_MASK,
|
||||
MAX98926_DAI_BSEL_32);
|
||||
break;
|
||||
case 48:
|
||||
regmap_update_bits(max98926->regmap,
|
||||
MAX98926_DAI_CLK_MODE2,
|
||||
MAX98926_DAI_BSEL_MASK,
|
||||
MAX98926_DAI_BSEL_48);
|
||||
break;
|
||||
case 64:
|
||||
regmap_update_bits(max98926->regmap,
|
||||
MAX98926_DAI_CLK_MODE2,
|
||||
MAX98926_DAI_BSEL_MASK,
|
||||
MAX98926_DAI_BSEL_64);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* find the closest rate */
|
||||
for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
|
||||
if (rate_table[i].rate >= rate) {
|
||||
dai_sr = rate_table[i].sr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (dai_sr < 0)
|
||||
return -EINVAL;
|
||||
|
||||
/* set DAI_SR to correct LRCLK frequency */
|
||||
regmap_update_bits(max98926->regmap,
|
||||
MAX98926_DAI_CLK_MODE2,
|
||||
MAX98926_DAI_SR_MASK, dai_sr << MAX98926_DAI_SR_SHIFT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define MAX98926_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
|
||||
|
||||
static struct snd_soc_dai_ops max98926_dai_ops = {
|
||||
.set_fmt = max98926_dai_set_fmt,
|
||||
.hw_params = max98926_dai_hw_params,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver max98926_dai[] = {
|
||||
{
|
||||
.name = "max98926-aif1",
|
||||
.playback = {
|
||||
.stream_name = "HiFi Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_8000_48000,
|
||||
.formats = MAX98926_FORMATS,
|
||||
},
|
||||
.capture = {
|
||||
.stream_name = "HiFi Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_8000_48000,
|
||||
.formats = MAX98926_FORMATS,
|
||||
},
|
||||
.ops = &max98926_dai_ops,
|
||||
}
|
||||
};
|
||||
|
||||
static int max98926_probe(struct snd_soc_codec *codec)
|
||||
{
|
||||
struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
|
||||
|
||||
max98926->codec = codec;
|
||||
codec->control_data = max98926->regmap;
|
||||
/* Hi-Z all the slots */
|
||||
regmap_write(max98926->regmap, MAX98926_DOUT_HIZ_CFG4, 0xF0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct snd_soc_codec_driver soc_codec_dev_max98926 = {
|
||||
.probe = max98926_probe,
|
||||
.controls = max98926_snd_controls,
|
||||
.num_controls = ARRAY_SIZE(max98926_snd_controls),
|
||||
.dapm_routes = max98926_audio_map,
|
||||
.num_dapm_routes = ARRAY_SIZE(max98926_audio_map),
|
||||
.dapm_widgets = max98926_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(max98926_dapm_widgets),
|
||||
};
|
||||
|
||||
static struct regmap_config max98926_regmap = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.max_register = MAX98926_VERSION,
|
||||
.reg_defaults = max98926_reg,
|
||||
.num_reg_defaults = ARRAY_SIZE(max98926_reg),
|
||||
.volatile_reg = max98926_volatile_register,
|
||||
.readable_reg = max98926_readable_register,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
};
|
||||
|
||||
static int max98926_i2c_probe(struct i2c_client *i2c,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
int ret, reg;
|
||||
u32 value;
|
||||
struct max98926_priv *max98926;
|
||||
|
||||
max98926 = devm_kzalloc(&i2c->dev,
|
||||
sizeof(*max98926), GFP_KERNEL);
|
||||
if (!max98926)
|
||||
return -ENOMEM;
|
||||
|
||||
i2c_set_clientdata(i2c, max98926);
|
||||
max98926->regmap = devm_regmap_init_i2c(i2c, &max98926_regmap);
|
||||
if (IS_ERR(max98926->regmap)) {
|
||||
ret = PTR_ERR(max98926->regmap);
|
||||
dev_err(&i2c->dev,
|
||||
"Failed to allocate regmap: %d\n", ret);
|
||||
goto err_out;
|
||||
}
|
||||
if (of_property_read_bool(i2c->dev.of_node, "interleave-mode"))
|
||||
max98926->interleave_mode = true;
|
||||
|
||||
if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
|
||||
if (value > MAX98926_DAI_VMON_SLOT_1E_1F) {
|
||||
dev_err(&i2c->dev, "vmon slot number is wrong:\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
max98926->v_slot = value;
|
||||
}
|
||||
if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
|
||||
if (value > MAX98926_DAI_IMON_SLOT_1E_1F) {
|
||||
dev_err(&i2c->dev, "imon slot number is wrong:\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
max98926->i_slot = value;
|
||||
}
|
||||
ret = regmap_read(max98926->regmap,
|
||||
MAX98926_VERSION, ®);
|
||||
if (ret < 0) {
|
||||
dev_err(&i2c->dev, "Failed to read: %x\n", reg);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98926,
|
||||
max98926_dai, ARRAY_SIZE(max98926_dai));
|
||||
if (ret < 0)
|
||||
dev_err(&i2c->dev,
|
||||
"Failed to register codec: %d\n", ret);
|
||||
dev_info(&i2c->dev, "device version: %x\n", reg);
|
||||
err_out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int max98926_i2c_remove(struct i2c_client *client)
|
||||
{
|
||||
snd_soc_unregister_codec(&client->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id max98926_i2c_id[] = {
|
||||
{ "max98926", 0 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, max98926_i2c_id);
|
||||
|
||||
static const struct of_device_id max98926_of_match[] = {
|
||||
{ .compatible = "maxim,max98926", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, max98926_of_match);
|
||||
|
||||
static struct i2c_driver max98926_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "max98926",
|
||||
.of_match_table = of_match_ptr(max98926_of_match),
|
||||
.pm = NULL,
|
||||
},
|
||||
.probe = max98926_i2c_probe,
|
||||
.remove = max98926_i2c_remove,
|
||||
.id_table = max98926_i2c_id,
|
||||
};
|
||||
|
||||
module_i2c_driver(max98926_i2c_driver)
|
||||
MODULE_DESCRIPTION("ALSA SoC MAX98926 driver");
|
||||
MODULE_AUTHOR("Anish kumar <anish.kumar@maximintegrated.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
848
sound/soc/codecs/max98926.h
Normal file
848
sound/soc/codecs/max98926.h
Normal file
@ -0,0 +1,848 @@
|
||||
/*
|
||||
* max98926.h -- MAX98926 ALSA SoC Audio driver
|
||||
* Copyright 2013-2015 Maxim Integrated Products
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _MAX98926_H
|
||||
#define _MAX98926_H
|
||||
|
||||
#define MAX98926_CHIP_VERSION 0x40
|
||||
#define MAX98926_CHIP_VERSION1 0x50
|
||||
|
||||
#define MAX98926_VBAT_DATA 0x00
|
||||
#define MAX98926_VBST_DATA 0x01
|
||||
#define MAX98926_LIVE_STATUS0 0x02
|
||||
#define MAX98926_LIVE_STATUS1 0x03
|
||||
#define MAX98926_LIVE_STATUS2 0x04
|
||||
#define MAX98926_STATE0 0x05
|
||||
#define MAX98926_STATE1 0x06
|
||||
#define MAX98926_STATE2 0x07
|
||||
#define MAX98926_FLAG0 0x08
|
||||
#define MAX98926_FLAG1 0x09
|
||||
#define MAX98926_FLAG2 0x0A
|
||||
#define MAX98926_IRQ_ENABLE0 0x0B
|
||||
#define MAX98926_IRQ_ENABLE1 0x0C
|
||||
#define MAX98926_IRQ_ENABLE2 0x0D
|
||||
#define MAX98926_IRQ_CLEAR0 0x0E
|
||||
#define MAX98926_IRQ_CLEAR1 0x0F
|
||||
#define MAX98926_IRQ_CLEAR2 0x10
|
||||
#define MAX98926_MAP0 0x11
|
||||
#define MAX98926_MAP1 0x12
|
||||
#define MAX98926_MAP2 0x13
|
||||
#define MAX98926_MAP3 0x14
|
||||
#define MAX98926_MAP4 0x15
|
||||
#define MAX98926_MAP5 0x16
|
||||
#define MAX98926_MAP6 0x17
|
||||
#define MAX98926_MAP7 0x18
|
||||
#define MAX98926_MAP8 0x19
|
||||
#define MAX98926_DAI_CLK_MODE1 0x1A
|
||||
#define MAX98926_DAI_CLK_MODE2 0x1B
|
||||
#define MAX98926_DAI_CLK_DIV_M_MSBS 0x1C
|
||||
#define MAX98926_DAI_CLK_DIV_M_LSBS 0x1D
|
||||
#define MAX98926_DAI_CLK_DIV_N_MSBS 0x1E
|
||||
#define MAX98926_DAI_CLK_DIV_N_LSBS 0x1F
|
||||
#define MAX98926_FORMAT 0x20
|
||||
#define MAX98926_TDM_SLOT_SELECT 0x21
|
||||
#define MAX98926_DOUT_CFG_VMON 0x22
|
||||
#define MAX98926_DOUT_CFG_IMON 0x23
|
||||
#define MAX98926_DOUT_CFG_VBAT 0x24
|
||||
#define MAX98926_DOUT_CFG_VBST 0x25
|
||||
#define MAX98926_DOUT_CFG_FLAG 0x26
|
||||
#define MAX98926_DOUT_HIZ_CFG1 0x27
|
||||
#define MAX98926_DOUT_HIZ_CFG2 0x28
|
||||
#define MAX98926_DOUT_HIZ_CFG3 0x29
|
||||
#define MAX98926_DOUT_HIZ_CFG4 0x2A
|
||||
#define MAX98926_DOUT_DRV_STRENGTH 0x2B
|
||||
#define MAX98926_FILTERS 0x2C
|
||||
#define MAX98926_GAIN 0x2D
|
||||
#define MAX98926_GAIN_RAMPING 0x2E
|
||||
#define MAX98926_SPK_AMP 0x2F
|
||||
#define MAX98926_THRESHOLD 0x30
|
||||
#define MAX98926_ALC_ATTACK 0x31
|
||||
#define MAX98926_ALC_ATTEN_RLS 0x32
|
||||
#define MAX98926_ALC_HOLD_RLS 0x33
|
||||
#define MAX98926_ALC_CONFIGURATION 0x34
|
||||
#define MAX98926_BOOST_CONVERTER 0x35
|
||||
#define MAX98926_BLOCK_ENABLE 0x36
|
||||
#define MAX98926_CONFIGURATION 0x37
|
||||
#define MAX98926_GLOBAL_ENABLE 0x38
|
||||
#define MAX98926_BOOST_LIMITER 0x3A
|
||||
#define MAX98926_VERSION 0xFF
|
||||
|
||||
#define MAX98926_REG_CNT (MAX98926_R03A_BOOST_LIMITER+1)
|
||||
|
||||
#define MAX98926_PDM_CURRENT_MASK (1<<7)
|
||||
#define MAX98926_PDM_CURRENT_SHIFT 7
|
||||
#define MAX98926_PDM_VOLTAGE_MASK (1<<3)
|
||||
#define MAX98926_PDM_VOLTAGE_SHIFT 3
|
||||
#define MAX98926_PDM_CHANNEL_0_MASK (1<<2)
|
||||
#define MAX98926_PDM_CHANNEL_0_SHIFT 2
|
||||
#define MAX98926_PDM_CHANNEL_1_MASK (1<<6)
|
||||
#define MAX98926_PDM_CHANNEL_1_SHIFT 6
|
||||
#define MAX98926_PDM_CHANNEL_1_HIZ 5
|
||||
#define MAX98926_PDM_CHANNEL_0_HIZ 1
|
||||
#define MAX98926_PDM_SOURCE_0_SHIFT 0
|
||||
#define MAX98926_PDM_SOURCE_0_MASK (1<<0)
|
||||
#define MAX98926_PDM_SOURCE_1_MASK (1<<4)
|
||||
#define MAX98926_PDM_SOURCE_1_SHIFT 4
|
||||
|
||||
/* MAX98926 Register Bit Fields */
|
||||
|
||||
/* MAX98926_R002_LIVE_STATUS0 */
|
||||
#define MAX98926_THERMWARN_STATUS_MASK (1<<3)
|
||||
#define MAX98926_THERMWARN_STATUS_SHIFT 3
|
||||
#define MAX98926_THERMWARN_STATUS_WIDTH 1
|
||||
#define MAX98926_THERMSHDN_STATUS_MASK (1<<1)
|
||||
#define MAX98926_THERMSHDN_STATUS_SHIFT 1
|
||||
#define MAX98926_THERMSHDN_STATUS_WIDTH 1
|
||||
|
||||
/* MAX98926_R003_LIVE_STATUS1 */
|
||||
#define MAX98926_SPKCURNT_STATUS_MASK (1<<5)
|
||||
#define MAX98926_SPKCURNT_STATUS_SHIFT 5
|
||||
#define MAX98926_SPKCURNT_STATUS_WIDTH 1
|
||||
#define MAX98926_WATCHFAIL_STATUS_MASK (1<<4)
|
||||
#define MAX98926_WATCHFAIL_STATUS_SHIFT 4
|
||||
#define MAX98926_WATCHFAIL_STATUS_WIDTH 1
|
||||
#define MAX98926_ALCINFH_STATUS_MASK (1<<3)
|
||||
#define MAX98926_ALCINFH_STATUS_SHIFT 3
|
||||
#define MAX98926_ALCINFH_STATUS_WIDTH 1
|
||||
#define MAX98926_ALCACT_STATUS_MASK (1<<2)
|
||||
#define MAX98926_ALCACT_STATUS_SHIFT 2
|
||||
#define MAX98926_ALCACT_STATUS_WIDTH 1
|
||||
#define MAX98926_ALCMUT_STATUS_MASK (1<<1)
|
||||
#define MAX98926_ALCMUT_STATUS_SHIFT 1
|
||||
#define MAX98926_ALCMUT_STATUS_WIDTH 1
|
||||
#define MAX98926_ACLP_STATUS_MASK (1<<0)
|
||||
#define MAX98926_ACLP_STATUS_SHIFT 0
|
||||
#define MAX98926_ACLP_STATUS_WIDTH 1
|
||||
|
||||
/* MAX98926_R004_LIVE_STATUS2 */
|
||||
#define MAX98926_SLOTOVRN_STATUS_MASK (1<<6)
|
||||
#define MAX98926_SLOTOVRN_STATUS_SHIFT 6
|
||||
#define MAX98926_SLOTOVRN_STATUS_WIDTH 1
|
||||
#define MAX98926_INVALSLOT_STATUS_MASK (1<<5)
|
||||
#define MAX98926_INVALSLOT_STATUS_SHIFT 5
|
||||
#define MAX98926_INVALSLOT_STATUS_WIDTH 1
|
||||
#define MAX98926_SLOTCNFLT_STATUS_MASK (1<<4)
|
||||
#define MAX98926_SLOTCNFLT_STATUS_SHIFT 4
|
||||
#define MAX98926_SLOTCNFLT_STATUS_WIDTH 1
|
||||
#define MAX98926_VBSTOVFL_STATUS_MASK (1<<3)
|
||||
#define MAX98926_VBSTOVFL_STATUS_SHIFT 3
|
||||
#define MAX98926_VBSTOVFL_STATUS_WIDTH 1
|
||||
#define MAX98926_VBATOVFL_STATUS_MASK (1<<2)
|
||||
#define MAX98926_VBATOVFL_STATUS_SHIFT 2
|
||||
#define MAX98926_VBATOVFL_STATUS_WIDTH 1
|
||||
#define MAX98926_IMONOVFL_STATUS_MASK (1<<1)
|
||||
#define MAX98926_IMONOVFL_STATUS_SHIFT 1
|
||||
#define MAX98926_IMONOVFL_STATUS_WIDTH 1
|
||||
#define MAX98926_VMONOVFL_STATUS_MASK (1<<0)
|
||||
#define MAX98926_VMONOVFL_STATUS_SHIFT 0
|
||||
#define MAX98926_VMONOVFL_STATUS_WIDTH 1
|
||||
|
||||
/* MAX98926_R005_STATE0 */
|
||||
#define MAX98926_THERMWARN_END_STATE_MASK (1<<3)
|
||||
#define MAX98926_THERMWARN_END_STATE_SHIFT 3
|
||||
#define MAX98926_THERMWARN_END_STATE_WIDTH 1
|
||||
#define MAX98926_THERMWARN_BGN_STATE_MASK (1<<2)
|
||||
#define MAX98926_THERMWARN_BGN_STATE_SHIFT 1
|
||||
#define MAX98926_THERMWARN_BGN_STATE_WIDTH 1
|
||||
#define MAX98926_THERMSHDN_END_STATE_MASK (1<<1)
|
||||
#define MAX98926_THERMSHDN_END_STATE_SHIFT 1
|
||||
#define MAX98926_THERMSHDN_END_STATE_WIDTH 1
|
||||
#define MAX98926_THERMSHDN_BGN_STATE_MASK (1<<0)
|
||||
#define MAX98926_THERMSHDN_BGN_STATE_SHIFT 0
|
||||
#define MAX98926_THERMSHDN_BGN_STATE_WIDTH 1
|
||||
|
||||
/* MAX98926_R006_STATE1 */
|
||||
#define MAX98926_SPRCURNT_STATE_MASK (1<<5)
|
||||
#define MAX98926_SPRCURNT_STATE_SHIFT 5
|
||||
#define MAX98926_SPRCURNT_STATE_WIDTH 1
|
||||
#define MAX98926_WATCHFAIL_STATE_MASK (1<<4)
|
||||
#define MAX98926_WATCHFAIL_STATE_SHIFT 4
|
||||
#define MAX98926_WATCHFAIL_STATE_WIDTH 1
|
||||
#define MAX98926_ALCINFH_STATE_MASK (1<<3)
|
||||
#define MAX98926_ALCINFH_STATE_SHIFT 3
|
||||
#define MAX98926_ALCINFH_STATE_WIDTH 1
|
||||
#define MAX98926_ALCACT_STATE_MASK (1<<2)
|
||||
#define MAX98926_ALCACT_STATE_SHIFT 2
|
||||
#define MAX98926_ALCACT_STATE_WIDTH 1
|
||||
#define MAX98926_ALCMUT_STATE_MASK (1<<1)
|
||||
#define MAX98926_ALCMUT_STATE_SHIFT 1
|
||||
#define MAX98926_ALCMUT_STATE_WIDTH 1
|
||||
#define MAX98926_ALCP_STATE_MASK (1<<0)
|
||||
#define MAX98926_ALCP_STATE_SHIFT 0
|
||||
#define MAX98926_ALCP_STATE_WIDTH 1
|
||||
|
||||
/* MAX98926_R007_STATE2 */
|
||||
#define MAX98926_SLOTOVRN_STATE_MASK (1<<6)
|
||||
#define MAX98926_SLOTOVRN_STATE_SHIFT 6
|
||||
#define MAX98926_SLOTOVRN_STATE_WIDTH 1
|
||||
#define MAX98926_INVALSLOT_STATE_MASK (1<<5)
|
||||
#define MAX98926_INVALSLOT_STATE_SHIFT 5
|
||||
#define MAX98926_INVALSLOT_STATE_WIDTH 1
|
||||
#define MAX98926_SLOTCNFLT_STATE_MASK (1<<4)
|
||||
#define MAX98926_SLOTCNFLT_STATE_SHIFT 4
|
||||
#define MAX98926_SLOTCNFLT_STATE_WIDTH 1
|
||||
#define MAX98926_VBSTOVFL_STATE_MASK (1<<3)
|
||||
#define MAX98926_VBSTOVFL_STATE_SHIFT 3
|
||||
#define MAX98926_VBSTOVFL_STATE_WIDTH 1
|
||||
#define MAX98926_VBATOVFL_STATE_MASK (1<<2)
|
||||
#define MAX98926_VBATOVFL_STATE_SHIFT 2
|
||||
#define MAX98926_VBATOVFL_STATE_WIDTH 1
|
||||
#define MAX98926_IMONOVFL_STATE_MASK (1<<1)
|
||||
#define MAX98926_IMONOVFL_STATE_SHIFT 1
|
||||
#define MAX98926_IMONOVFL_STATE_WIDTH 1
|
||||
#define MAX98926_VMONOVFL_STATE_MASK (1<<0)
|
||||
#define MAX98926_VMONOVFL_STATE_SHIFT 0
|
||||
#define MAX98926_VMONOVFL_STATE_WIDTH 1
|
||||
|
||||
/* MAX98926_R008_FLAG0 */
|
||||
#define MAX98926_THERMWARN_END_FLAG_MASK (1<<3)
|
||||
#define MAX98926_THERMWARN_END_FLAG_SHIFT 3
|
||||
#define MAX98926_THERMWARN_END_FLAG_WIDTH 1
|
||||
#define MAX98926_THERMWARN_BGN_FLAG_MASK (1<<2)
|
||||
#define MAX98926_THERMWARN_BGN_FLAG_SHIFT 2
|
||||
#define MAX98926_THERMWARN_BGN_FLAG_WIDTH 1
|
||||
#define MAX98926_THERMSHDN_END_FLAG_MASK (1<<1)
|
||||
#define MAX98926_THERMSHDN_END_FLAG_SHIFT 1
|
||||
#define MAX98926_THERMSHDN_END_FLAG_WIDTH 1
|
||||
#define MAX98926_THERMSHDN_BGN_FLAG_MASK (1<<0)
|
||||
#define MAX98926_THERMSHDN_BGN_FLAG_SHIFT 0
|
||||
#define MAX98926_THERMSHDN_BGN_FLAG_WIDTH 1
|
||||
|
||||
/* MAX98926_R009_FLAG1 */
|
||||
#define MAX98926_SPKCURNT_FLAG_MASK (1<<5)
|
||||
#define MAX98926_SPKCURNT_FLAG_SHIFT 5
|
||||
#define MAX98926_SPKCURNT_FLAG_WIDTH 1
|
||||
#define MAX98926_WATCHFAIL_FLAG_MASK (1<<4)
|
||||
#define MAX98926_WATCHFAIL_FLAG_SHIFT 4
|
||||
#define MAX98926_WATCHFAIL_FLAG_WIDTH 1
|
||||
#define MAX98926_ALCINFH_FLAG_MASK (1<<3)
|
||||
#define MAX98926_ALCINFH_FLAG_SHIFT 3
|
||||
#define MAX98926_ALCINFH_FLAG_WIDTH 1
|
||||
#define MAX98926_ALCACT_FLAG_MASK (1<<2)
|
||||
#define MAX98926_ALCACT_FLAG_SHIFT 2
|
||||
#define MAX98926_ALCACT_FLAG_WIDTH 1
|
||||
#define MAX98926_ALCMUT_FLAG_MASK (1<<1)
|
||||
#define MAX98926_ALCMUT_FLAG_SHIFT 1
|
||||
#define MAX98926_ALCMUT_FLAG_WIDTH 1
|
||||
#define MAX98926_ALCP_FLAG_MASK (1<<0)
|
||||
#define MAX98926_ALCP_FLAG_SHIFT 0
|
||||
#define MAX98926_ALCP_FLAG_WIDTH 1
|
||||
|
||||
/* MAX98926_R00A_FLAG2 */
|
||||
#define MAX98926_SLOTOVRN_FLAG_MASK (1<<6)
|
||||
#define MAX98926_SLOTOVRN_FLAG_SHIFT 6
|
||||
#define MAX98926_SLOTOVRN_FLAG_WIDTH 1
|
||||
#define MAX98926_INVALSLOT_FLAG_MASK (1<<5)
|
||||
#define MAX98926_INVALSLOT_FLAG_SHIFT 5
|
||||
#define MAX98926_INVALSLOT_FLAG_WIDTH 1
|
||||
#define MAX98926_SLOTCNFLT_FLAG_MASK (1<<4)
|
||||
#define MAX98926_SLOTCNFLT_FLAG_SHIFT 4
|
||||
#define MAX98926_SLOTCNFLT_FLAG_WIDTH 1
|
||||
#define MAX98926_VBSTOVFL_FLAG_MASK (1<<3)
|
||||
#define MAX98926_VBSTOVFL_FLAG_SHIFT 3
|
||||
#define MAX98926_VBSTOVFL_FLAG_WIDTH 1
|
||||
#define MAX98926_VBATOVFL_FLAG_MASK (1<<2)
|
||||
#define MAX98926_VBATOVFL_FLAG_SHIFT 2
|
||||
#define MAX98926_VBATOVFL_FLAG_WIDTH 1
|
||||
#define MAX98926_IMONOVFL_FLAG_MASK (1<<1)
|
||||
#define MAX98926_IMONOVFL_FLAG_SHIFT 1
|
||||
#define MAX98926_IMONOVFL_FLAG_WIDTH 1
|
||||
#define MAX98926_VMONOVFL_FLAG_MASK (1<<0)
|
||||
#define MAX98926_VMONOVFL_FLAG_SHIFT 0
|
||||
#define MAX98926_VMONOVFL_FLAG_WIDTH 1
|
||||
|
||||
/* MAX98926_R00B_IRQ_ENABLE0 */
|
||||
#define MAX98926_THERMWARN_END_EN_MASK (1<<3)
|
||||
#define MAX98926_THERMWARN_END_EN_SHIFT 3
|
||||
#define MAX98926_THERMWARN_END_EN_WIDTH 1
|
||||
#define MAX98926_THERMWARN_BGN_EN_MASK (1<<2)
|
||||
#define MAX98926_THERMWARN_BGN_EN_SHIFT 2
|
||||
#define MAX98926_THERMWARN_BGN_EN_WIDTH 1
|
||||
#define MAX98926_THERMSHDN_END_EN_MASK (1<<1)
|
||||
#define MAX98926_THERMSHDN_END_EN_SHIFT 1
|
||||
#define MAX98926_THERMSHDN_END_EN_WIDTH 1
|
||||
#define MAX98926_THERMSHDN_BGN_EN_MASK (1<<0)
|
||||
#define MAX98926_THERMSHDN_BGN_EN_SHIFT 0
|
||||
#define MAX98926_THERMSHDN_BGN_EN_WIDTH 1
|
||||
|
||||
/* MAX98926_R00C_IRQ_ENABLE1 */
|
||||
#define MAX98926_SPKCURNT_EN_MASK (1<<5)
|
||||
#define MAX98926_SPKCURNT_EN_SHIFT 5
|
||||
#define MAX98926_SPKCURNT_EN_WIDTH 1
|
||||
#define MAX98926_WATCHFAIL_EN_MASK (1<<4)
|
||||
#define MAX98926_WATCHFAIL_EN_SHIFT 4
|
||||
#define MAX98926_WATCHFAIL_EN_WIDTH 1
|
||||
#define MAX98926_ALCINFH_EN_MASK (1<<3)
|
||||
#define MAX98926_ALCINFH_EN_SHIFT 3
|
||||
#define MAX98926_ALCINFH_EN_WIDTH 1
|
||||
#define MAX98926_ALCACT_EN_MASK (1<<2)
|
||||
#define MAX98926_ALCACT_EN_SHIFT 2
|
||||
#define MAX98926_ALCACT_EN_WIDTH 1
|
||||
#define MAX98926_ALCMUT_EN_MASK (1<<1)
|
||||
#define MAX98926_ALCMUT_EN_SHIFT 1
|
||||
#define MAX98926_ALCMUT_EN_WIDTH 1
|
||||
#define MAX98926_ALCP_EN_MASK (1<<0)
|
||||
#define MAX98926_ALCP_EN_SHIFT 0
|
||||
#define MAX98926_ALCP_EN_WIDTH 1
|
||||
|
||||
/* MAX98926_R00D_IRQ_ENABLE2 */
|
||||
#define MAX98926_SLOTOVRN_EN_MASK (1<<6)
|
||||
#define MAX98926_SLOTOVRN_EN_SHIFT 6
|
||||
#define MAX98926_SLOTOVRN_EN_WIDTH 1
|
||||
#define MAX98926_INVALSLOT_EN_MASK (1<<5)
|
||||
#define MAX98926_INVALSLOT_EN_SHIFT 5
|
||||
#define MAX98926_INVALSLOT_EN_WIDTH 1
|
||||
#define MAX98926_SLOTCNFLT_EN_MASK (1<<4)
|
||||
#define MAX98926_SLOTCNFLT_EN_SHIFT 4
|
||||
#define MAX98926_SLOTCNFLT_EN_WIDTH 1
|
||||
#define MAX98926_VBSTOVFL_EN_MASK (1<<3)
|
||||
#define MAX98926_VBSTOVFL_EN_SHIFT 3
|
||||
#define MAX98926_VBSTOVFL_EN_WIDTH 1
|
||||
#define MAX98926_VBATOVFL_EN_MASK (1<<2)
|
||||
#define MAX98926_VBATOVFL_EN_SHIFT 2
|
||||
#define MAX98926_VBATOVFL_EN_WIDTH 1
|
||||
#define MAX98926_IMONOVFL_EN_MASK (1<<1)
|
||||
#define MAX98926_IMONOVFL_EN_SHIFT 1
|
||||
#define MAX98926_IMONOVFL_EN_WIDTH 1
|
||||
#define MAX98926_VMONOVFL_EN_MASK (1<<0)
|
||||
#define MAX98926_VMONOVFL_EN_SHIFT 0
|
||||
#define MAX98926_VMONOVFL_EN_WIDTH 1
|
||||
|
||||
/* MAX98926_R00E_IRQ_CLEAR0 */
|
||||
#define MAX98926_THERMWARN_END_CLR_MASK (1<<3)
|
||||
#define MAX98926_THERMWARN_END_CLR_SHIFT 3
|
||||
#define MAX98926_THERMWARN_END_CLR_WIDTH 1
|
||||
#define MAX98926_THERMWARN_BGN_CLR_MASK (1<<2)
|
||||
#define MAX98926_THERMWARN_BGN_CLR_SHIFT 2
|
||||
#define MAX98926_THERMWARN_BGN_CLR_WIDTH 1
|
||||
#define MAX98926_THERMSHDN_END_CLR_MASK (1<<1)
|
||||
#define MAX98926_THERMSHDN_END_CLR_SHIFT 1
|
||||
#define MAX98926_THERMSHDN_END_CLR_WIDTH 1
|
||||
#define MAX98926_THERMSHDN_BGN_CLR_MASK (1<<0)
|
||||
#define MAX98926_THERMSHDN_BGN_CLR_SHIFT 0
|
||||
#define MAX98926_THERMSHDN_BGN_CLR_WIDTH 1
|
||||
|
||||
/* MAX98926_R00F_IRQ_CLEAR1 */
|
||||
#define MAX98926_SPKCURNT_CLR_MASK (1<<5)
|
||||
#define MAX98926_SPKCURNT_CLR_SHIFT 5
|
||||
#define MAX98926_SPKCURNT_CLR_WIDTH 1
|
||||
#define MAX98926_WATCHFAIL_CLR_MASK (1<<4)
|
||||
#define MAX98926_WATCHFAIL_CLR_SHIFT 4
|
||||
#define MAX98926_WATCHFAIL_CLR_WIDTH 1
|
||||
#define MAX98926_ALCINFH_CLR_MASK (1<<3)
|
||||
#define MAX98926_ALCINFH_CLR_SHIFT 3
|
||||
#define MAX98926_ALCINFH_CLR_WIDTH 1
|
||||
#define MAX98926_ALCACT_CLR_MASK (1<<2)
|
||||
#define MAX98926_ALCACT_CLR_SHIFT 2
|
||||
#define MAX98926_ALCACT_CLR_WIDTH 1
|
||||
#define MAX98926_ALCMUT_CLR_MASK (1<<1)
|
||||
#define MAX98926_ALCMUT_CLR_SHIFT 1
|
||||
#define MAX98926_ALCMUT_CLR_WIDTH 1
|
||||
#define MAX98926_ALCP_CLR_MASK (1<<0)
|
||||
#define MAX98926_ALCP_CLR_SHIFT 0
|
||||
#define MAX98926_ALCP_CLR_WIDTH 1
|
||||
|
||||
/* MAX98926_R010_IRQ_CLEAR2 */
|
||||
#define MAX98926_SLOTOVRN_CLR_MASK (1<<6)
|
||||
#define MAX98926_SLOTOVRN_CLR_SHIFT 6
|
||||
#define MAX98926_SLOTOVRN_CLR_WIDTH 1
|
||||
#define MAX98926_INVALSLOT_CLR_MASK (1<<5)
|
||||
#define MAX98926_INVALSLOT_CLR_SHIFT 5
|
||||
#define MAX98926_INVALSLOT_CLR_WIDTH 1
|
||||
#define MAX98926_SLOTCNFLT_CLR_MASK (1<<4)
|
||||
#define MAX98926_SLOTCNFLT_CLR_SHIFT 4
|
||||
#define MAX98926_SLOTCNFLT_CLR_WIDTH 1
|
||||
#define MAX98926_VBSTOVFL_CLR_MASK (1<<3)
|
||||
#define MAX98926_VBSTOVFL_CLR_SHIFT 3
|
||||
#define MAX98926_VBSTOVFL_CLR_WIDTH 1
|
||||
#define MAX98926_VBATOVFL_CLR_MASK (1<<2)
|
||||
#define MAX98926_VBATOVFL_CLR_SHIFT 2
|
||||
#define MAX98926_VBATOVFL_CLR_WIDTH 1
|
||||
#define MAX98926_IMONOVFL_CLR_MASK (1<<1)
|
||||
#define MAX98926_IMONOVFL_CLR_SHIFT 1
|
||||
#define MAX98926_IMONOVFL_CLR_WIDTH 1
|
||||
#define MAX98926_VMONOVFL_CLR_MASK (1<<0)
|
||||
#define MAX98926_VMONOVFL_CLR_SHIFT 0
|
||||
#define MAX98926_VMONOVFL_CLR_WIDTH 1
|
||||
|
||||
/* MAX98926_R011_MAP0 */
|
||||
#define MAX98926_ER_THERMWARN_EN_MASK (1<<7)
|
||||
#define MAX98926_ER_THERMWARN_EN_SHIFT 7
|
||||
#define MAX98926_ER_THERMWARN_EN_WIDTH 1
|
||||
#define MAX98926_ER_THERMWARN_MAP_MASK (0x07<<4)
|
||||
#define MAX98926_ER_THERMWARN_MAP_SHIFT 4
|
||||
#define MAX98926_ER_THERMWARN_MAP_WIDTH 3
|
||||
|
||||
/* MAX98926_R012_MAP1 */
|
||||
#define MAX98926_ER_ALCMUT_EN_MASK (1<<7)
|
||||
#define MAX98926_ER_ALCMUT_EN_SHIFT 7
|
||||
#define MAX98926_ER_ALCMUT_EN_WIDTH 1
|
||||
#define MAX98926_ER_ALCMUT_MAP_MASK (0x07<<4)
|
||||
#define MAX98926_ER_ALCMUT_MAP_SHIFT 4
|
||||
#define MAX98926_ER_ALCMUT_MAP_WIDTH 3
|
||||
#define MAX98926_ER_ALCP_EN_MASK (1<<3)
|
||||
#define MAX98926_ER_ALCP_EN_SHIFT 3
|
||||
#define MAX98926_ER_ALCP_EN_WIDTH 1
|
||||
#define MAX98926_ER_ALCP_MAP_MASK (0x07<<0)
|
||||
#define MAX98926_ER_ALCP_MAP_SHIFT 0
|
||||
#define MAX98926_ER_ALCP_MAP_WIDTH 3
|
||||
|
||||
/* MAX98926_R013_MAP2 */
|
||||
#define MAX98926_ER_ALCINFH_EN_MASK (1<<7)
|
||||
#define MAX98926_ER_ALCINFH_EN_SHIFT 7
|
||||
#define MAX98926_ER_ALCINFH_EN_WIDTH 1
|
||||
#define MAX98926_ER_ALCINFH_MAP_MASK (0x07<<4)
|
||||
#define MAX98926_ER_ALCINFH_MAP_SHIFT 4
|
||||
#define MAX98926_ER_ALCINFH_MAP_WIDTH 3
|
||||
#define MAX98926_ER_ALCACT_EN_MASK (1<<3)
|
||||
#define MAX98926_ER_ALCACT_EN_SHIFT 3
|
||||
#define MAX98926_ER_ALCACT_EN_WIDTH 1
|
||||
#define MAX98926_ER_ALCACT_MAP_MASK (0x07<<0)
|
||||
#define MAX98926_ER_ALCACT_MAP_SHIFT 0
|
||||
#define MAX98926_ER_ALCACT_MAP_WIDTH 3
|
||||
|
||||
/* MAX98926_R014_MAP3 */
|
||||
#define MAX98926_ER_SPKCURNT_EN_MASK (1<<7)
|
||||
#define MAX98926_ER_SPKCURNT_EN_SHIFT 7
|
||||
#define MAX98926_ER_SPKCURNT_EN_WIDTH 1
|
||||
#define MAX98926_ER_SPKCURNT_MAP_MASK (0x07<<4)
|
||||
#define MAX98926_ER_SPKCURNT_MAP_SHIFT 4
|
||||
#define MAX98926_ER_SPKCURNT_MAP_WIDTH 3
|
||||
|
||||
/* MAX98926_R015_MAP4 */
|
||||
/* RESERVED */
|
||||
|
||||
/* MAX98926_R016_MAP5 */
|
||||
#define MAX98926_ER_IMONOVFL_EN_MASK (1<<7)
|
||||
#define MAX98926_ER_IMONOVFL_EN_SHIFT 7
|
||||
#define MAX98926_ER_IMONOVFL_EN_WIDTH 1
|
||||
#define MAX98926_ER_IMONOVFL_MAP_MASK (0x07<<4)
|
||||
#define MAX98926_ER_IMONOVFL_MAP_SHIFT 4
|
||||
#define MAX98926_ER_IMONOVFL_MAP_WIDTH 3
|
||||
#define MAX98926_ER_VMONOVFL_EN_MASK (1<<3)
|
||||
#define MAX98926_ER_VMONOVFL_EN_SHIFT 3
|
||||
#define MAX98926_ER_VMONOVFL_EN_WIDTH 1
|
||||
#define MAX98926_ER_VMONOVFL_MAP_MASK (0x07<<0)
|
||||
#define MAX98926_ER_VMONOVFL_MAP_SHIFT 0
|
||||
#define MAX98926_ER_VMONOVFL_MAP_WIDTH 3
|
||||
|
||||
/* MAX98926_R017_MAP6 */
|
||||
#define MAX98926_ER_VBSTOVFL_EN_MASK (1<<7)
|
||||
#define MAX98926_ER_VBSTOVFL_EN_SHIFT 7
|
||||
#define MAX98926_ER_VBSTOVFL_EN_WIDTH 1
|
||||
#define MAX98926_ER_VBSTOVFL_MAP_MASK (0x07<<4)
|
||||
#define MAX98926_ER_VBSTOVFL_MAP_SHIFT 4
|
||||
#define MAX98926_ER_VBSTOVFL_MAP_WIDTH 3
|
||||
#define MAX98926_ER_VBATOVFL_EN_MASK (1<<3)
|
||||
#define MAX98926_ER_VBATOVFL_EN_SHIFT 3
|
||||
#define MAX98926_ER_VBATOVFL_EN_WIDTH 1
|
||||
#define MAX98926_ER_VBATOVFL_MAP_MASK (0x07<<0)
|
||||
#define MAX98926_ER_VBATOVFL_MAP_SHIFT 0
|
||||
#define MAX98926_ER_VBATOVFL_MAP_WIDTH 3
|
||||
|
||||
/* MAX98926_R018_MAP7 */
|
||||
#define MAX98926_ER_INVALSLOT_EN_MASK (1<<7)
|
||||
#define MAX98926_ER_INVALSLOT_EN_SHIFT 7
|
||||
#define MAX98926_ER_INVALSLOT_EN_WIDTH 1
|
||||
#define MAX98926_ER_INVALSLOT_MAP_MASK (0x07<<4)
|
||||
#define MAX98926_ER_INVALSLOT_MAP_SHIFT 4
|
||||
#define MAX98926_ER_INVALSLOT_MAP_WIDTH 3
|
||||
#define MAX98926_ER_SLOTCNFLT_EN_MASK (1<<3)
|
||||
#define MAX98926_ER_SLOTCNFLT_EN_SHIFT 3
|
||||
#define MAX98926_ER_SLOTCNFLT_EN_WIDTH 1
|
||||
#define MAX98926_ER_SLOTCNFLT_MAP_MASK (0x07<<0)
|
||||
#define MAX98926_ER_SLOTCNFLT_MAP_SHIFT 0
|
||||
#define MAX98926_ER_SLOTCNFLT_MAP_WIDTH 3
|
||||
|
||||
/* MAX98926_R019_MAP8 */
|
||||
#define MAX98926_ER_SLOTOVRN_EN_MASK (1<<3)
|
||||
#define MAX98926_ER_SLOTOVRN_EN_SHIFT 3
|
||||
#define MAX98926_ER_SLOTOVRN_EN_WIDTH 1
|
||||
#define MAX98926_ER_SLOTOVRN_MAP_MASK (0x07<<0)
|
||||
#define MAX98926_ER_SLOTOVRN_MAP_SHIFT 0
|
||||
#define MAX98926_ER_SLOTOVRN_MAP_WIDTH 3
|
||||
|
||||
/* MAX98926_R01A_DAI_CLK_MODE1 */
|
||||
#define MAX98926_DAI_CLK_SOURCE_MASK (1<<6)
|
||||
#define MAX98926_DAI_CLK_SOURCE_SHIFT 6
|
||||
#define MAX98926_DAI_CLK_SOURCE_WIDTH 1
|
||||
#define MAX98926_MDLL_MULT_MASK (0x0F<<0)
|
||||
#define MAX98926_MDLL_MULT_SHIFT 0
|
||||
#define MAX98926_MDLL_MULT_WIDTH 4
|
||||
|
||||
#define MAX98926_MDLL_MULT_MCLKx8 6
|
||||
#define MAX98926_MDLL_MULT_MCLKx16 8
|
||||
|
||||
/* MAX98926_R01B_DAI_CLK_MODE2 */
|
||||
#define MAX98926_DAI_SR_MASK (0x0F<<4)
|
||||
#define MAX98926_DAI_SR_SHIFT 4
|
||||
#define MAX98926_DAI_SR_WIDTH 4
|
||||
#define MAX98926_DAI_MAS_MASK (1<<3)
|
||||
#define MAX98926_DAI_MAS_SHIFT 3
|
||||
#define MAX98926_DAI_MAS_WIDTH 1
|
||||
#define MAX98926_DAI_BSEL_MASK (0x07<<0)
|
||||
#define MAX98926_DAI_BSEL_SHIFT 0
|
||||
#define MAX98926_DAI_BSEL_WIDTH 3
|
||||
|
||||
#define MAX98926_DAI_BSEL_32 (0 << MAX98926_DAI_BSEL_SHIFT)
|
||||
#define MAX98926_DAI_BSEL_48 (1 << MAX98926_DAI_BSEL_SHIFT)
|
||||
#define MAX98926_DAI_BSEL_64 (2 << MAX98926_DAI_BSEL_SHIFT)
|
||||
#define MAX98926_DAI_BSEL_256 (6 << MAX98926_DAI_BSEL_SHIFT)
|
||||
|
||||
/* MAX98926_R01C_DAI_CLK_DIV_M_MSBS */
|
||||
#define MAX98926_DAI_M_MSBS_MASK (0xFF<<0)
|
||||
#define MAX98926_DAI_M_MSBS_SHIFT 0
|
||||
#define MAX98926_DAI_M_MSBS_WIDTH 8
|
||||
|
||||
/* MAX98926_R01D_DAI_CLK_DIV_M_LSBS */
|
||||
#define MAX98926_DAI_M_LSBS_MASK (0xFF<<0)
|
||||
#define MAX98926_DAI_M_LSBS_SHIFT 0
|
||||
#define MAX98926_DAI_M_LSBS_WIDTH 8
|
||||
|
||||
/* MAX98926_R01E_DAI_CLK_DIV_N_MSBS */
|
||||
#define MAX98926_DAI_N_MSBS_MASK (0x7F<<0)
|
||||
#define MAX98926_DAI_N_MSBS_SHIFT 0
|
||||
#define MAX98926_DAI_N_MSBS_WIDTH 7
|
||||
|
||||
/* MAX98926_R01F_DAI_CLK_DIV_N_LSBS */
|
||||
#define MAX98926_DAI_N_LSBS_MASK (0xFF<<0)
|
||||
#define MAX98926_DAI_N_LSBS_SHIFT 0
|
||||
#define MAX98926_DAI_N_LSBS_WIDTH 8
|
||||
|
||||
/* MAX98926_R020_FORMAT */
|
||||
#define MAX98926_DAI_CHANSZ_MASK (0x03<<6)
|
||||
#define MAX98926_DAI_CHANSZ_SHIFT 6
|
||||
#define MAX98926_DAI_CHANSZ_WIDTH 2
|
||||
#define MAX98926_DAI_INTERLEAVE_MASK (1<<5)
|
||||
#define MAX98926_DAI_INTERLEAVE_SHIFT 5
|
||||
#define MAX98926_DAI_INTERLEAVE_WIDTH 1
|
||||
#define MAX98926_DAI_EXTBCLK_HIZ_MASK (1<<4)
|
||||
#define MAX98926_DAI_EXTBCLK_HIZ_SHIFT 4
|
||||
#define MAX98926_DAI_EXTBCLK_HIZ_WIDTH 1
|
||||
#define MAX98926_DAI_WCI_MASK (1<<3)
|
||||
#define MAX98926_DAI_WCI_SHIFT 3
|
||||
#define MAX98926_DAI_WCI_WIDTH 1
|
||||
#define MAX98926_DAI_BCI_MASK (1<<2)
|
||||
#define MAX98926_DAI_BCI_SHIFT 2
|
||||
#define MAX98926_DAI_BCI_WIDTH 1
|
||||
#define MAX98926_DAI_DLY_MASK (1<<1)
|
||||
#define MAX98926_DAI_DLY_SHIFT 1
|
||||
#define MAX98926_DAI_DLY_WIDTH 1
|
||||
#define MAX98926_DAI_TDM_MASK (1<<0)
|
||||
#define MAX98926_DAI_TDM_SHIFT 0
|
||||
#define MAX98926_DAI_TDM_WIDTH 1
|
||||
|
||||
#define MAX98926_DAI_CHANSZ_16 (1 << MAX98926_DAI_CHANSZ_SHIFT)
|
||||
#define MAX98926_DAI_CHANSZ_24 (2 << MAX98926_DAI_CHANSZ_SHIFT)
|
||||
#define MAX98926_DAI_CHANSZ_32 (3 << MAX98926_DAI_CHANSZ_SHIFT)
|
||||
|
||||
/* MAX98926_R021_TDM_SLOT_SELECT */
|
||||
#define MAX98926_DAI_DO_EN_MASK (1<<7)
|
||||
#define MAX98926_DAI_DO_EN_SHIFT 7
|
||||
#define MAX98926_DAI_DO_EN_WIDTH 1
|
||||
#define MAX98926_DAI_DIN_EN_MASK (1<<6)
|
||||
#define MAX98926_DAI_DIN_EN_SHIFT 6
|
||||
#define MAX98926_DAI_DIN_EN_WIDTH 1
|
||||
#define MAX98926_DAI_INR_SOURCE_MASK (0x07<<3)
|
||||
#define MAX98926_DAI_INR_SOURCE_SHIFT 3
|
||||
#define MAX98926_DAI_INR_SOURCE_WIDTH 3
|
||||
#define MAX98926_DAI_INL_SOURCE_MASK (0x07<<0)
|
||||
#define MAX98926_DAI_INL_SOURCE_SHIFT 0
|
||||
#define MAX98926_DAI_INL_SOURCE_WIDTH 3
|
||||
|
||||
/* MAX98926_R022_DOUT_CFG_VMON */
|
||||
#define MAX98926_DAI_VMON_EN_MASK (1<<5)
|
||||
#define MAX98926_DAI_VMON_EN_SHIFT 5
|
||||
#define MAX98926_DAI_VMON_EN_WIDTH 1
|
||||
#define MAX98926_DAI_VMON_SLOT_MASK (0x1F<<0)
|
||||
#define MAX98926_DAI_VMON_SLOT_SHIFT 0
|
||||
#define MAX98926_DAI_VMON_SLOT_WIDTH 5
|
||||
|
||||
#define MAX98926_DAI_VMON_SLOT_00_01 (0 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_01_02 (1 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_02_03 (2 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_03_04 (3 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_04_05 (4 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_05_06 (5 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_06_07 (6 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_07_08 (7 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_08_09 (8 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_09_0A (9 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_0A_0B (10 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_0B_0C (11 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_0C_0D (12 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_0D_0E (13 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_0E_0F (14 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_0F_10 (15 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_10_11 (16 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_11_12 (17 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_12_13 (18 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_13_14 (19 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_14_15 (20 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_15_16 (21 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_16_17 (22 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_17_18 (23 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_18_19 (24 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_19_1A (25 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_1A_1B (26 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_1B_1C (27 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_1C_1D (28 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_1D_1E (29 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_VMON_SLOT_1E_1F (30 << MAX98926_DAI_VMON_SLOT_SHIFT)
|
||||
|
||||
/* MAX98926_R023_DOUT_CFG_IMON */
|
||||
#define MAX98926_DAI_IMON_EN_MASK (1<<5)
|
||||
#define MAX98926_DAI_IMON_EN_SHIFT 5
|
||||
#define MAX98926_DAI_IMON_EN_WIDTH 1
|
||||
#define MAX98926_DAI_IMON_SLOT_MASK (0x1F<<0)
|
||||
#define MAX98926_DAI_IMON_SLOT_SHIFT 0
|
||||
#define MAX98926_DAI_IMON_SLOT_WIDTH 5
|
||||
|
||||
#define MAX98926_DAI_IMON_SLOT_00_01 (0 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_01_02 (1 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_02_03 (2 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_03_04 (3 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_04_05 (4 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_05_06 (5 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_06_07 (6 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_07_08 (7 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_08_09 (8 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_09_0A (9 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_0A_0B (10 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_0B_0C (11 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_0C_0D (12 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_0D_0E (13 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_0E_0F (14 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_0F_10 (15 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_10_11 (16 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_11_12 (17 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_12_13 (18 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_13_14 (19 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_14_15 (20 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_15_16 (21 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_16_17 (22 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_17_18 (23 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_18_19 (24 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_19_1A (25 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_1A_1B (26 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_1B_1C (27 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_1C_1D (28 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_1D_1E (29 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
#define MAX98926_DAI_IMON_SLOT_1E_1F (30 << MAX98926_DAI_IMON_SLOT_SHIFT)
|
||||
|
||||
/* MAX98926_R024_DOUT_CFG_VBAT */
|
||||
#define MAX98926_DAI_INTERLEAVE_SLOT_MASK (0x1F<<0)
|
||||
#define MAX98926_DAI_INTERLEAVE_SLOT_SHIFT 0
|
||||
#define MAX98926_DAI_INTERLEAVE_SLOT_WIDTH 5
|
||||
|
||||
/* MAX98926_R025_DOUT_CFG_VBST */
|
||||
#define MAX98926_DAI_VBST_EN_MASK (1<<5)
|
||||
#define MAX98926_DAI_VBST_EN_SHIFT 5
|
||||
#define MAX98926_DAI_VBST_EN_WIDTH 1
|
||||
#define MAX98926_DAI_VBST_SLOT_MASK (0x1F<<0)
|
||||
#define MAX98926_DAI_VBST_SLOT_SHIFT 0
|
||||
#define MAX98926_DAI_VBST_SLOT_WIDTH 5
|
||||
|
||||
/* MAX98926_R026_DOUT_CFG_FLAG */
|
||||
#define MAX98926_DAI_FLAG_EN_MASK (1<<5)
|
||||
#define MAX98926_DAI_FLAG_EN_SHIFT 5
|
||||
#define MAX98926_DAI_FLAG_EN_WIDTH 1
|
||||
#define MAX98926_DAI_FLAG_SLOT_MASK (0x1F<<0)
|
||||
#define MAX98926_DAI_FLAG_SLOT_SHIFT 0
|
||||
#define MAX98926_DAI_FLAG_SLOT_WIDTH 5
|
||||
|
||||
/* MAX98926_R027_DOUT_HIZ_CFG1 */
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0)
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG1_SHIFT 0
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG1_WIDTH 8
|
||||
|
||||
/* MAX98926_R028_DOUT_HIZ_CFG2 */
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0)
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG2_SHIFT 0
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG2_WIDTH 8
|
||||
|
||||
/* MAX98926_R029_DOUT_HIZ_CFG3 */
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0)
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG3_SHIFT 0
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG3_WIDTH 8
|
||||
|
||||
/* MAX98926_R02A_DOUT_HIZ_CFG4 */
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0)
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG4_SHIFT 0
|
||||
#define MAX98926_DAI_SLOT_HIZ_CFG4_WIDTH 8
|
||||
|
||||
/* MAX98926_R02B_DOUT_DRV_STRENGTH */
|
||||
#define MAX98926_DAI_OUT_DRIVE_MASK (0x03<<0)
|
||||
#define MAX98926_DAI_OUT_DRIVE_SHIFT 0
|
||||
#define MAX98926_DAI_OUT_DRIVE_WIDTH 2
|
||||
|
||||
/* MAX98926_R02C_FILTERS */
|
||||
#define MAX98926_ADC_DITHER_EN_MASK (1<<7)
|
||||
#define MAX98926_ADC_DITHER_EN_SHIFT 7
|
||||
#define MAX98926_ADC_DITHER_EN_WIDTH 1
|
||||
#define MAX98926_IV_DCB_EN_MASK (1<<6)
|
||||
#define MAX98926_IV_DCB_EN_SHIFT 6
|
||||
#define MAX98926_IV_DCB_EN_WIDTH 1
|
||||
#define MAX98926_DAC_DITHER_EN_MASK (1<<4)
|
||||
#define MAX98926_DAC_DITHER_EN_SHIFT 4
|
||||
#define MAX98926_DAC_DITHER_EN_WIDTH 1
|
||||
#define MAX98926_DAC_FILTER_MODE_MASK (1<<3)
|
||||
#define MAX98926_DAC_FILTER_MODE_SHIFT 3
|
||||
#define MAX98926_DAC_FILTER_MODE_WIDTH 1
|
||||
#define MAX98926_DAC_HPF_MASK (0x07<<0)
|
||||
#define MAX98926_DAC_HPF_SHIFT 0
|
||||
#define MAX98926_DAC_HPF_WIDTH 3
|
||||
#define MAX98926_DAC_HPF_DISABLE (0 << MAX98926_DAC_HPF_SHIFT)
|
||||
#define MAX98926_DAC_HPF_DC_BLOCK (1 << MAX98926_DAC_HPF_SHIFT)
|
||||
#define MAX98926_DAC_HPF_EN_100 (2 << MAX98926_DAC_HPF_SHIFT)
|
||||
#define MAX98926_DAC_HPF_EN_200 (3 << MAX98926_DAC_HPF_SHIFT)
|
||||
#define MAX98926_DAC_HPF_EN_400 (4 << MAX98926_DAC_HPF_SHIFT)
|
||||
#define MAX98926_DAC_HPF_EN_800 (5 << MAX98926_DAC_HPF_SHIFT)
|
||||
|
||||
/* MAX98926_R02D_GAIN */
|
||||
#define MAX98926_DAC_IN_SEL_MASK (0x03<<5)
|
||||
#define MAX98926_DAC_IN_SEL_SHIFT 5
|
||||
#define MAX98926_DAC_IN_SEL_WIDTH 2
|
||||
#define MAX98926_SPK_GAIN_MASK (0x1F<<0)
|
||||
#define MAX98926_SPK_GAIN_SHIFT 0
|
||||
#define MAX98926_SPK_GAIN_WIDTH 5
|
||||
|
||||
#define MAX98926_DAC_IN_SEL_LEFT_DAI (0 << MAX98926_DAC_IN_SEL_SHIFT)
|
||||
#define MAX98926_DAC_IN_SEL_RIGHT_DAI (1 << MAX98926_DAC_IN_SEL_SHIFT)
|
||||
#define MAX98926_DAC_IN_SEL_SUMMED_DAI (2 << MAX98926_DAC_IN_SEL_SHIFT)
|
||||
#define MAX98926_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << MAX98926_DAC_IN_SEL_SHIFT)
|
||||
|
||||
/* MAX98926_R02E_GAIN_RAMPING */
|
||||
#define MAX98926_SPK_RMP_EN_MASK (1<<1)
|
||||
#define MAX98926_SPK_RMP_EN_SHIFT 1
|
||||
#define MAX98926_SPK_RMP_EN_WIDTH 1
|
||||
#define MAX98926_SPK_ZCD_EN_MASK (1<<0)
|
||||
#define MAX98926_SPK_ZCD_EN_SHIFT 0
|
||||
#define MAX98926_SPK_ZCD_EN_WIDTH 1
|
||||
|
||||
/* MAX98926_R02F_SPK_AMP */
|
||||
#define MAX98926_SPK_MODE_MASK (1<<0)
|
||||
#define MAX98926_SPK_MODE_SHIFT 0
|
||||
#define MAX98926_SPK_MODE_WIDTH 1
|
||||
#define MAX98926_INSELECT_MODE_MASK (1<<1)
|
||||
#define MAX98926_INSELECT_MODE_SHIFT 1
|
||||
#define MAX98926_INSELECT_MODE_WIDTH 1
|
||||
|
||||
/* MAX98926_R030_THRESHOLD */
|
||||
#define MAX98926_ALC_EN_MASK (1<<5)
|
||||
#define MAX98926_ALC_EN_SHIFT 5
|
||||
#define MAX98926_ALC_EN_WIDTH 1
|
||||
#define MAX98926_ALC_TH_MASK (0x1F<<0)
|
||||
#define MAX98926_ALC_TH_SHIFT 0
|
||||
#define MAX98926_ALC_TH_WIDTH 5
|
||||
|
||||
/* MAX98926_R031_ALC_ATTACK */
|
||||
#define MAX98926_ALC_ATK_STEP_MASK (0x0F<<4)
|
||||
#define MAX98926_ALC_ATK_STEP_SHIFT 4
|
||||
#define MAX98926_ALC_ATK_STEP_WIDTH 4
|
||||
#define MAX98926_ALC_ATK_RATE_MASK (0x7<<0)
|
||||
#define MAX98926_ALC_ATK_RATE_SHIFT 0
|
||||
#define MAX98926_ALC_ATK_RATE_WIDTH 3
|
||||
|
||||
/* MAX98926_R032_ALC_ATTEN_RLS */
|
||||
#define MAX98926_ALC_MAX_ATTEN_MASK (0x0F<<4)
|
||||
#define MAX98926_ALC_MAX_ATTEN_SHIFT 4
|
||||
#define MAX98926_ALC_MAX_ATTEN_WIDTH 4
|
||||
#define MAX98926_ALC_RLS_RATE_MASK (0x7<<0)
|
||||
#define MAX98926_ALC_RLS_RATE_SHIFT 0
|
||||
#define MAX98926_ALC_RLS_RATE_WIDTH 3
|
||||
|
||||
/* MAX98926_R033_ALC_HOLD_RLS */
|
||||
#define MAX98926_ALC_RLS_TGR_MASK (1<<0)
|
||||
#define MAX98926_ALC_RLS_TGR_SHIFT 0
|
||||
#define MAX98926_ALC_RLS_TGR_WIDTH 1
|
||||
|
||||
/* MAX98926_R034_ALC_CONFIGURATION */
|
||||
#define MAX98926_ALC_MUTE_EN_MASK (1<<7)
|
||||
#define MAX98926_ALC_MUTE_EN_SHIFT 7
|
||||
#define MAX98926_ALC_MUTE_EN_WIDTH 1
|
||||
#define MAX98926_ALC_MUTE_DLY_MASK (0x07<<4)
|
||||
#define MAX98926_ALC_MUTE_DLY_SHIFT 4
|
||||
#define MAX98926_ALC_MUTE_DLY_WIDTH 3
|
||||
#define MAX98926_ALC_RLS_DBT_MASK (0x07<<0)
|
||||
#define MAX98926_ALC_RLS_DBT_SHIFT 0
|
||||
#define MAX98926_ALC_RLS_DBT_WIDTH 3
|
||||
|
||||
/* MAX98926_R035_BOOST_CONVERTER */
|
||||
#define MAX98926_BST_SYNC_MASK (1<<7)
|
||||
#define MAX98926_BST_SYNC_SHIFT 7
|
||||
#define MAX98926_BST_SYNC_WIDTH 1
|
||||
#define MAX98926_BST_PHASE_MASK (0x03<<4)
|
||||
#define MAX98926_BST_PHASE_SHIFT 4
|
||||
#define MAX98926_BST_PHASE_WIDTH 2
|
||||
#define MAX98926_BST_SKIP_MODE_MASK (0x03<<0)
|
||||
#define MAX98926_BST_SKIP_MODE_SHIFT 0
|
||||
#define MAX98926_BST_SKIP_MODE_WIDTH 2
|
||||
|
||||
/* MAX98926_R036_BLOCK_ENABLE */
|
||||
#define MAX98926_BST_EN_MASK (1<<7)
|
||||
#define MAX98926_BST_EN_SHIFT 7
|
||||
#define MAX98926_BST_EN_WIDTH 1
|
||||
#define MAX98926_WATCH_EN_MASK (1<<6)
|
||||
#define MAX98926_WATCH_EN_SHIFT 6
|
||||
#define MAX98926_WATCH_EN_WIDTH 1
|
||||
#define MAX98926_CLKMON_EN_MASK (1<<5)
|
||||
#define MAX98926_CLKMON_EN_SHIFT 5
|
||||
#define MAX98926_CLKMON_EN_WIDTH 1
|
||||
#define MAX98926_SPK_EN_MASK (1<<4)
|
||||
#define MAX98926_SPK_EN_SHIFT 4
|
||||
#define MAX98926_SPK_EN_WIDTH 1
|
||||
#define MAX98926_ADC_VBST_EN_MASK (1<<3)
|
||||
#define MAX98926_ADC_VBST_EN_SHIFT 3
|
||||
#define MAX98926_ADC_VBST_EN_WIDTH 1
|
||||
#define MAX98926_ADC_VBAT_EN_MASK (1<<2)
|
||||
#define MAX98926_ADC_VBAT_EN_SHIFT 2
|
||||
#define MAX98926_ADC_VBAT_EN_WIDTH 1
|
||||
#define MAX98926_ADC_IMON_EN_MASK (1<<1)
|
||||
#define MAX98926_ADC_IMON_EN_SHIFT 1
|
||||
#define MAX98926_ADC_IMON_EN_WIDTH 1
|
||||
#define MAX98926_ADC_VMON_EN_MASK (1<<0)
|
||||
#define MAX98926_ADC_VMON_EN_SHIFT 0
|
||||
#define MAX98926_ADC_VMON_EN_WIDTH 1
|
||||
|
||||
/* MAX98926_R037_CONFIGURATION */
|
||||
#define MAX98926_BST_VOUT_MASK (0x0F<<4)
|
||||
#define MAX98926_BST_VOUT_SHIFT 4
|
||||
#define MAX98926_BST_VOUT_WIDTH 4
|
||||
#define MAX98926_THERMWARN_LEVEL_MASK (0x03<<2)
|
||||
#define MAX98926_THERMWARN_LEVEL_SHIFT 2
|
||||
#define MAX98926_THERMWARN_LEVEL_WIDTH 2
|
||||
#define MAX98926_WATCH_TIME_MASK (0x03<<0)
|
||||
#define MAX98926_WATCH_TIME_SHIFT 0
|
||||
#define MAX98926_WATCH_TIME_WIDTH 2
|
||||
|
||||
/* MAX98926_R038_GLOBAL_ENABLE */
|
||||
#define MAX98926_EN_MASK (1<<7)
|
||||
#define MAX98926_EN_SHIFT 7
|
||||
#define MAX98926_EN_WIDTH 1
|
||||
|
||||
/* MAX98926_R03A_BOOST_LIMITER */
|
||||
#define MAX98926_BST_ILIM_MASK (0xF<<4)
|
||||
#define MAX98926_BST_ILIM_SHIFT 4
|
||||
#define MAX98926_BST_ILIM_WIDTH 4
|
||||
|
||||
/* MAX98926_R0FF_VERSION */
|
||||
#define MAX98926_REV_ID_MASK (0xFF<<0)
|
||||
#define MAX98926_REV_ID_SHIFT 0
|
||||
#define MAX98926_REV_ID_WIDTH 8
|
||||
|
||||
struct max98926_priv {
|
||||
struct regmap *regmap;
|
||||
struct snd_soc_codec *codec;
|
||||
unsigned int sysclk;
|
||||
unsigned int v_slot;
|
||||
unsigned int i_slot;
|
||||
unsigned int ch_size;
|
||||
unsigned int interleave_mode;
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user