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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-03-08 18:43:28 +07:00
drm/amdgpu: clean up asic level reset for VI
Drop soft reset, always use pci config reset. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
ceb5bc861e
commit
a2c5c69825
@ -571,374 +571,12 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
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return -EINVAL;
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}
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static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
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{
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dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(mmGRBM_STATUS));
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dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
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RREG32(mmGRBM_STATUS2));
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dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(mmGRBM_STATUS_SE0));
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dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(mmGRBM_STATUS_SE1));
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dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
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RREG32(mmGRBM_STATUS_SE2));
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dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
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RREG32(mmGRBM_STATUS_SE3));
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dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(mmSRBM_STATUS));
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dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
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RREG32(mmSRBM_STATUS2));
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dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
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RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
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if (adev->sdma.num_instances > 1) {
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dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
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RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
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}
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dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
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dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
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RREG32(mmCP_STALLED_STAT1));
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dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
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RREG32(mmCP_STALLED_STAT2));
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dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
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RREG32(mmCP_STALLED_STAT3));
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dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
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RREG32(mmCP_CPF_BUSY_STAT));
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dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
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RREG32(mmCP_CPF_STALLED_STAT1));
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dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
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dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
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dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
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RREG32(mmCP_CPC_STALLED_STAT1));
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dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
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}
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/**
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* vi_gpu_check_soft_reset - check which blocks are busy
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*
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* @adev: amdgpu_device pointer
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*
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* Check which blocks are busy and return the relevant reset
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* mask to be used by vi_gpu_soft_reset().
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* Returns a mask of the blocks to be reset.
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*/
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u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
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{
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u32 reset_mask = 0;
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u32 tmp;
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/* GRBM_STATUS */
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tmp = RREG32(mmGRBM_STATUS);
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if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
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GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
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GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
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GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
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GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
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GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
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reset_mask |= AMDGPU_RESET_GFX;
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if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
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reset_mask |= AMDGPU_RESET_CP;
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/* GRBM_STATUS2 */
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tmp = RREG32(mmGRBM_STATUS2);
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if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
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reset_mask |= AMDGPU_RESET_RLC;
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if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK |
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GRBM_STATUS2__CPC_BUSY_MASK |
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GRBM_STATUS2__CPG_BUSY_MASK))
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reset_mask |= AMDGPU_RESET_CP;
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/* SRBM_STATUS2 */
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tmp = RREG32(mmSRBM_STATUS2);
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if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
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reset_mask |= AMDGPU_RESET_DMA;
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if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
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reset_mask |= AMDGPU_RESET_DMA1;
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/* SRBM_STATUS */
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tmp = RREG32(mmSRBM_STATUS);
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if (tmp & SRBM_STATUS__IH_BUSY_MASK)
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reset_mask |= AMDGPU_RESET_IH;
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if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
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reset_mask |= AMDGPU_RESET_SEM;
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if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
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reset_mask |= AMDGPU_RESET_GRBM;
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if (adev->asic_type != CHIP_TOPAZ) {
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if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK |
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SRBM_STATUS__UVD_BUSY_MASK))
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reset_mask |= AMDGPU_RESET_UVD;
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}
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if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
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reset_mask |= AMDGPU_RESET_VMC;
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if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
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SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
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reset_mask |= AMDGPU_RESET_MC;
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/* SDMA0_STATUS_REG */
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tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
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if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
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reset_mask |= AMDGPU_RESET_DMA;
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/* SDMA1_STATUS_REG */
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if (adev->sdma.num_instances > 1) {
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tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
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if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
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reset_mask |= AMDGPU_RESET_DMA1;
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}
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#if 0
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/* VCE_STATUS */
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if (adev->asic_type != CHIP_TOPAZ) {
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tmp = RREG32(mmVCE_STATUS);
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if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK)
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reset_mask |= AMDGPU_RESET_VCE;
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if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK)
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reset_mask |= AMDGPU_RESET_VCE1;
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}
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if (adev->asic_type != CHIP_TOPAZ) {
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if (amdgpu_display_is_display_hung(adev))
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reset_mask |= AMDGPU_RESET_DISPLAY;
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}
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#endif
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/* Skip MC reset as it's mostly likely not hung, just busy */
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if (reset_mask & AMDGPU_RESET_MC) {
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DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
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reset_mask &= ~AMDGPU_RESET_MC;
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}
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return reset_mask;
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}
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/**
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* vi_gpu_soft_reset - soft reset GPU
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*
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* @adev: amdgpu_device pointer
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* @reset_mask: mask of which blocks to reset
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*
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* Soft reset the blocks specified in @reset_mask.
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*/
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static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
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{
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struct amdgpu_mode_mc_save save;
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u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
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u32 tmp;
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if (reset_mask == 0)
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return;
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dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
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vi_print_gpu_status_regs(adev);
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dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
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RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
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dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
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/* disable CG/PG */
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/* stop the rlc */
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//XXX
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//gfx_v8_0_rlc_stop(adev);
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/* Disable GFX parsing/prefetching */
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tmp = RREG32(mmCP_ME_CNTL);
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tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
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tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
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tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
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WREG32(mmCP_ME_CNTL, tmp);
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/* Disable MEC parsing/prefetching */
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tmp = RREG32(mmCP_MEC_CNTL);
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tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
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tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
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WREG32(mmCP_MEC_CNTL, tmp);
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if (reset_mask & AMDGPU_RESET_DMA) {
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/* sdma0 */
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tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
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tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
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WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
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}
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if (reset_mask & AMDGPU_RESET_DMA1) {
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/* sdma1 */
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tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
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tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
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WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
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}
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gmc_v8_0_mc_stop(adev, &save);
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if (amdgpu_asic_wait_for_mc_idle(adev)) {
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dev_warn(adev->dev, "Wait for MC idle timedout !\n");
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}
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if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) {
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grbm_soft_reset =
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REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
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grbm_soft_reset =
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REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
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}
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if (reset_mask & AMDGPU_RESET_CP) {
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grbm_soft_reset =
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REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
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}
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if (reset_mask & AMDGPU_RESET_DMA)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1);
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if (reset_mask & AMDGPU_RESET_DMA1)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1);
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if (reset_mask & AMDGPU_RESET_DISPLAY)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1);
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if (reset_mask & AMDGPU_RESET_RLC)
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grbm_soft_reset =
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REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
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if (reset_mask & AMDGPU_RESET_SEM)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
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if (reset_mask & AMDGPU_RESET_IH)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1);
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if (reset_mask & AMDGPU_RESET_GRBM)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
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if (reset_mask & AMDGPU_RESET_VMC)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
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if (reset_mask & AMDGPU_RESET_UVD)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
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if (reset_mask & AMDGPU_RESET_VCE)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
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if (reset_mask & AMDGPU_RESET_VCE)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
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if (!(adev->flags & AMD_IS_APU)) {
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if (reset_mask & AMDGPU_RESET_MC)
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srbm_soft_reset =
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REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
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}
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if (grbm_soft_reset) {
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tmp = RREG32(mmGRBM_SOFT_RESET);
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tmp |= grbm_soft_reset;
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dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmGRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmGRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~grbm_soft_reset;
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WREG32(mmGRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmGRBM_SOFT_RESET);
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}
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if (srbm_soft_reset) {
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tmp = RREG32(mmSRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~srbm_soft_reset;
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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}
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/* Wait a little for things to settle down */
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udelay(50);
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gmc_v8_0_mc_resume(adev, &save);
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udelay(50);
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vi_print_gpu_status_regs(adev);
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}
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static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
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{
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struct amdgpu_mode_mc_save save;
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u32 tmp, i;
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u32 i;
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dev_info(adev->dev, "GPU pci config reset\n");
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/* disable dpm? */
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/* disable cg/pg */
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/* Disable GFX parsing/prefetching */
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tmp = RREG32(mmCP_ME_CNTL);
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tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
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tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
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tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
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WREG32(mmCP_ME_CNTL, tmp);
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/* Disable MEC parsing/prefetching */
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tmp = RREG32(mmCP_MEC_CNTL);
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tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
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tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
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WREG32(mmCP_MEC_CNTL, tmp);
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/* Disable GFX parsing/prefetching */
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WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
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CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
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/* Disable MEC parsing/prefetching */
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WREG32(mmCP_MEC_CNTL,
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CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
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/* sdma0 */
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tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
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tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
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WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
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/* sdma1 */
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tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
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tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
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WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
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/* XXX other engines? */
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/* halt the rlc, disable cp internal ints */
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//XXX
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//gfx_v8_0_rlc_stop(adev);
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udelay(50);
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/* disable mem access */
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gmc_v8_0_mc_stop(adev, &save);
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if (amdgpu_asic_wait_for_mc_idle(adev)) {
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dev_warn(adev->dev, "Wait for MC idle timed out !\n");
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}
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/* disable BM */
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pci_clear_master(adev->pdev);
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/* reset */
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@ -978,26 +616,11 @@ static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hun
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*/
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static int vi_asic_reset(struct amdgpu_device *adev)
|
||||
{
|
||||
u32 reset_mask;
|
||||
vi_set_bios_scratch_engine_hung(adev, true);
|
||||
|
||||
reset_mask = vi_gpu_check_soft_reset(adev);
|
||||
vi_gpu_pci_config_reset(adev);
|
||||
|
||||
if (reset_mask)
|
||||
vi_set_bios_scratch_engine_hung(adev, true);
|
||||
|
||||
/* try soft reset */
|
||||
vi_gpu_soft_reset(adev, reset_mask);
|
||||
|
||||
reset_mask = vi_gpu_check_soft_reset(adev);
|
||||
|
||||
/* try pci config reset */
|
||||
if (reset_mask && amdgpu_hard_reset)
|
||||
vi_gpu_pci_config_reset(adev);
|
||||
|
||||
reset_mask = vi_gpu_check_soft_reset(adev);
|
||||
|
||||
if (!reset_mask)
|
||||
vi_set_bios_scratch_engine_hung(adev, false);
|
||||
vi_set_bios_scratch_engine_hung(adev, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user