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drm/i915: switch uncore mmio funcs to use intel_uncore
The full read/write ops can now work on the intel_uncore struct. Introduce intel_uncore_read/write functions working on intel_uncore and switch the I915_READ/WRITE macro to internally call those. v2: no change v3: add intel_uncore_read/write functions (Chris), update commit msg Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-6-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio
Chris Wilson
parent
eb17af67eb
commit
a2b4abfc62
@ -3476,18 +3476,21 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
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return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
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}
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#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
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#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
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#define __I915_REG_OP(op__, dev_priv__, ...) \
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intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
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#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
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#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
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#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
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#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
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#define I915_READ8(reg__) __I915_REG_OP(read8, dev_priv, (reg__))
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#define I915_WRITE8(reg__, val__) __I915_REG_OP(write8, dev_priv, (reg__), (val__))
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#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
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#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
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#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
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#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
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#define I915_READ16(reg__) __I915_REG_OP(read16, dev_priv, (reg__))
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#define I915_WRITE16(reg__, val__) __I915_REG_OP(write16, dev_priv, (reg__), (val__))
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#define I915_READ16_NOTRACE(reg__) __I915_REG_OP(read16_notrace, dev_priv, (reg__))
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#define I915_WRITE16_NOTRACE(reg__, val__) __I915_REG_OP(write16_notrace, dev_priv, (reg__), (val__))
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#define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
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#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
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#define I915_READ_NOTRACE(reg__) __I915_REG_OP(read_notrace, dev_priv, (reg__))
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#define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))
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/* Be very careful with read/write 64-bit values. On 32-bit machines, they
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* will be implemented using 2 32-bit writes in an arbitrary order with
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@ -3503,20 +3506,12 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
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*
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* You have been warned.
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*/
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#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
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#define I915_READ64(reg__) __I915_REG_OP(read64, dev_priv, (reg__))
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#define I915_READ64_2x32(lower_reg__, upper_reg__) \
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__I915_REG_OP(read64_2x32, dev_priv, (lower_reg__), (upper_reg__))
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#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
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u32 upper, lower, old_upper, loop = 0; \
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upper = I915_READ(upper_reg); \
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do { \
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old_upper = upper; \
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lower = I915_READ(lower_reg); \
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upper = I915_READ(upper_reg); \
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} while (upper != old_upper && loop++ < 2); \
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(u64)upper << 32 | lower; })
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#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
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#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
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#define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
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#define POSTING_READ16(reg__) __I915_REG_OP(posting_read16, dev_priv, (reg__))
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/* These are untraced mmio-accessors that are only valid to be used inside
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* critical sections, such as inside IRQ handlers, where forcewake is explicitly
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@ -3544,10 +3539,10 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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#define I915_READ_FW(reg__) __raw_uncore_read32(&dev_priv->uncore, (reg__))
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#define I915_WRITE_FW(reg__, val__) __raw_uncore_write32(&dev_priv->uncore, (reg__), (val__))
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#define I915_WRITE64_FW(reg__, val__) __raw_uncore_write64(&dev_priv->uncore, (reg__), (val__))
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#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
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#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
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#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
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#define I915_WRITE64_FW(reg__, val__) __I915_REG_OP(write64_fw, dev_priv, (reg__), (val__))
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#define POSTING_READ_FW(reg__) __I915_REG_OP(posting_read_fw, dev_priv, (reg__))
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/* "Broadcast RGB" property */
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#define INTEL_BROADCAST_RGB_AUTO 0
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@ -1093,7 +1093,6 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
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}
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#define GEN2_READ_HEADER(x) \
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struct intel_uncore *uncore = &dev_priv->uncore; \
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u##x val = 0; \
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__assert_rpm_wakelock_held(uncore->rpm);
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@ -1103,7 +1102,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
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#define __gen2_read(x) \
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static u##x \
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gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
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gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
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GEN2_READ_HEADER(x); \
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val = __raw_uncore_read##x(uncore, reg); \
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GEN2_READ_FOOTER; \
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@ -1111,7 +1110,7 @@ gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
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#define __gen5_read(x) \
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static u##x \
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gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
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gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
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GEN2_READ_HEADER(x); \
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ilk_dummy_write(uncore); \
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val = __raw_uncore_read##x(uncore, reg); \
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@ -1134,7 +1133,6 @@ __gen2_read(64)
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#undef GEN2_READ_HEADER
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#define GEN6_READ_HEADER(x) \
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struct intel_uncore *uncore = &dev_priv->uncore; \
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u32 offset = i915_mmio_reg_offset(reg); \
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unsigned long irqflags; \
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u##x val = 0; \
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@ -1178,7 +1176,7 @@ static inline void __force_wake_auto(struct intel_uncore *uncore,
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#define __gen_read(func, x) \
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static u##x \
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func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
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func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
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enum forcewake_domains fw_engine; \
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GEN6_READ_HEADER(x); \
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fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
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@ -1211,7 +1209,6 @@ __gen6_read(64)
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#undef GEN6_READ_HEADER
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#define GEN2_WRITE_HEADER \
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struct intel_uncore *uncore = &dev_priv->uncore; \
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trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
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__assert_rpm_wakelock_held(uncore->rpm); \
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@ -1219,7 +1216,7 @@ __gen6_read(64)
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#define __gen2_write(x) \
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static void \
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gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
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GEN2_WRITE_HEADER; \
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__raw_uncore_write##x(uncore, reg, val); \
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GEN2_WRITE_FOOTER; \
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@ -1227,7 +1224,7 @@ gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
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#define __gen5_write(x) \
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static void \
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gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
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GEN2_WRITE_HEADER; \
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ilk_dummy_write(uncore); \
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__raw_uncore_write##x(uncore, reg, val); \
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@ -1248,7 +1245,6 @@ __gen2_write(32)
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#undef GEN2_WRITE_HEADER
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#define GEN6_WRITE_HEADER \
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struct intel_uncore *uncore = &dev_priv->uncore; \
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u32 offset = i915_mmio_reg_offset(reg); \
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unsigned long irqflags; \
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trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
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@ -1262,7 +1258,7 @@ __gen2_write(32)
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#define __gen6_write(x) \
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static void \
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gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
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GEN6_WRITE_HEADER; \
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if (NEEDS_FORCE_WAKE(offset)) \
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__gen6_gt_wait_for_fifo(uncore); \
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@ -1272,7 +1268,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
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#define __gen_write(func, x) \
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static void \
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func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
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enum forcewake_domains fw_engine; \
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GEN6_WRITE_HEADER; \
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fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
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@ -69,20 +69,20 @@ struct intel_uncore_funcs {
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void (*force_wake_put)(struct intel_uncore *uncore,
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enum forcewake_domains domains);
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u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
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u8 (*mmio_readb)(struct intel_uncore *uncore,
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i915_reg_t r, bool trace);
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u16 (*mmio_readw)(struct drm_i915_private *dev_priv,
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u16 (*mmio_readw)(struct intel_uncore *uncore,
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i915_reg_t r, bool trace);
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u32 (*mmio_readl)(struct drm_i915_private *dev_priv,
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u32 (*mmio_readl)(struct intel_uncore *uncore,
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i915_reg_t r, bool trace);
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u64 (*mmio_readq)(struct drm_i915_private *dev_priv,
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u64 (*mmio_readq)(struct intel_uncore *uncore,
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i915_reg_t r, bool trace);
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void (*mmio_writeb)(struct drm_i915_private *dev_priv,
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void (*mmio_writeb)(struct intel_uncore *uncore,
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i915_reg_t r, u8 val, bool trace);
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void (*mmio_writew)(struct drm_i915_private *dev_priv,
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void (*mmio_writew)(struct intel_uncore *uncore,
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i915_reg_t r, u16 val, bool trace);
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void (*mmio_writel)(struct drm_i915_private *dev_priv,
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void (*mmio_writel)(struct intel_uncore *uncore,
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i915_reg_t r, u32 val, bool trace);
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};
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@ -275,6 +275,98 @@ __raw_write(64, q)
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#undef __raw_read
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#undef __raw_write
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#define __uncore_read(name__, x__, s__, trace__) \
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static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
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i915_reg_t reg) \
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{ \
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return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
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}
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#define __uncore_write(name__, x__, s__, trace__) \
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static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
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i915_reg_t reg, u##x__ val) \
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{ \
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uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
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}
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__uncore_read(read8, 8, b, true)
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__uncore_read(read16, 16, w, true)
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__uncore_read(read, 32, l, true)
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__uncore_read(read16_notrace, 16, w, false)
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__uncore_read(read_notrace, 32, l, false)
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__uncore_write(write8, 8, b, true)
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__uncore_write(write16, 16, w, true)
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__uncore_write(write, 32, l, true)
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__uncore_write(write_notrace, 32, l, false)
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/* Be very careful with read/write 64-bit values. On 32-bit machines, they
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* will be implemented using 2 32-bit writes in an arbitrary order with
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* an arbitrary delay between them. This can cause the hardware to
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* act upon the intermediate value, possibly leading to corruption and
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* machine death. For this reason we do not support I915_WRITE64, or
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* uncore->funcs.mmio_writeq.
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*
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* When reading a 64-bit value as two 32-bit values, the delay may cause
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* the two reads to mismatch, e.g. a timestamp overflowing. Also note that
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* occasionally a 64-bit register does not actually support a full readq
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* and must be read using two 32-bit reads.
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*
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* You have been warned.
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*/
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__uncore_read(read64, 64, q, true)
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static inline u64
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intel_uncore_read64_2x32(struct intel_uncore *uncore,
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i915_reg_t lower_reg, i915_reg_t upper_reg)
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{
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u32 upper, lower, old_upper, loop = 0;
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upper = intel_uncore_read(uncore, upper_reg);
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do {
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old_upper = upper;
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lower = intel_uncore_read(uncore, lower_reg);
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upper = intel_uncore_read(uncore, upper_reg);
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} while (upper != old_upper && loop++ < 2);
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return (u64)upper << 32 | lower;
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}
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#define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
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#define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
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#undef __uncore_read
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#undef __uncore_write
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/* These are untraced mmio-accessors that are only valid to be used inside
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* critical sections, such as inside IRQ handlers, where forcewake is explicitly
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* controlled.
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*
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* Think twice, and think again, before using these.
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*
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* As an example, these accessors can possibly be used between:
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*
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* spin_lock_irq(&uncore->lock);
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* intel_uncore_forcewake_get__locked();
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*
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* and
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*
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* intel_uncore_forcewake_put__locked();
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* spin_unlock_irq(&uncore->lock);
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*
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*
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* Note: some registers may not need forcewake held, so
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* intel_uncore_forcewake_{get,put} can be omitted, see
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* intel_uncore_forcewake_for_reg().
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*
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* Certain architectures will die if the same cacheline is concurrently accessed
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* by different clients (e.g. on Ivybridge). Access to registers should
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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#define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
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#define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
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#define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
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#define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
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#define raw_reg_read(base, reg) \
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readl(base + i915_mmio_reg_offset(reg))
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#define raw_reg_write(base, reg, value) \
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@ -26,14 +26,14 @@
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#define __nop_write(x) \
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static void \
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nop_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { }
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nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
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__nop_write(8)
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__nop_write(16)
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__nop_write(32)
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#define __nop_read(x) \
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static u##x \
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nop_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { return 0; }
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nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
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__nop_read(8)
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__nop_read(16)
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__nop_read(32)
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