A few OMAP clock & hwmod changes for v3.11.

Basic test logs are here:
 
 http://www.pwsan.com/omap/testlogs/prcm_devel_v3.11/20130609020805/
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Merge tag 'omap-devel-b-for-3.11' of http://git.kernel.org/cgit/linux/kernel/git/pjw/omap-pending into omap-for-v3.11/soc

A few OMAP clock & hwmod changes for v3.11.

Basic test logs are here:

http://www.pwsan.com/omap/testlogs/prcm_devel_v3.11/20130609020805/
This commit is contained in:
Tony Lindgren 2013-06-09 20:39:44 -07:00
commit a27b6da42a
4 changed files with 40 additions and 12 deletions

View File

@ -862,6 +862,33 @@ static struct clk_hw_omap wdt1_fck_hw = {
DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
static const char *pwmss_clk_parents[] = {
"dpll_per_m2_ck",
};
static const struct clk_ops ehrpwm_tbclk_ops = {
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
};
DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
NULL, NULL, 0,
AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
AM33XX_PWMSS0_TBCLKEN_SHIFT,
NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
NULL, NULL, 0,
AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
AM33XX_PWMSS1_TBCLKEN_SHIFT,
NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
NULL, NULL, 0,
AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
AM33XX_PWMSS2_TBCLKEN_SHIFT,
NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
/*
* clkdev
*/
@ -942,6 +969,9 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
};

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@ -3329,11 +3329,7 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
CLK(NULL, "cpefuse_fck", &cpefuse_fck),
CLK(NULL, "ts_fck", &ts_fck),
CLK(NULL, "usbtll_fck", &usbtll_fck),
CLK("usbhs_omap", "usbtll_fck", &usbtll_fck),
CLK("usbhs_tll", "usbtll_fck", &usbtll_fck),
CLK(NULL, "usbtll_ick", &usbtll_ick),
CLK("usbhs_omap", "usbtll_ick", &usbtll_ick),
CLK("usbhs_tll", "usbtll_ick", &usbtll_ick),
CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
CLK(NULL, "mmchs3_ick", &mmchs3_ick),
CLK(NULL, "mmchs3_fck", &mmchs3_fck),
@ -3343,7 +3339,6 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
CLK(NULL, "usbhost_ick", &usbhost_ick),
CLK("usbhs_omap", "usbhost_ick", &usbhost_ick),
};
/*
@ -3463,12 +3458,6 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "utmi_p2_gfclk", &dummy_ck),
CLK(NULL, "xclk60mhsp1_ck", &dummy_ck),
CLK(NULL, "xclk60mhsp2_ck", &dummy_ck),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck),
CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck),
CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
CLK(NULL, "init_60m_fclk", &dummy_ck),
CLK(NULL, "gpt1_fck", &gpt1_fck),
CLK(NULL, "aes2_ick", &aes2_ick),

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@ -358,6 +358,14 @@
#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
/* AM33XX PWMSS Control register */
#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664
/* AM33XX PWMSS Control bitfields */
#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0
#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1
#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2
/* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c

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@ -329,7 +329,7 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
};
static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
{ .name = "gfx", .rst_shift = 0 },
{ .name = "gfx", .rst_shift = 0, .st_shift = 0},
};
static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
.rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
.rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},