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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 02:56:47 +07:00
drm/i915: Split bxt_ddi_pll_select()
Split out of bxt_ddi_pll_select() the logic that calculates the pll dividers and dpll_hw_state into a new function that doesn't depend on crtc state. This will be used for enabling the port pll when doing upfront link training. v2: * Refactored code so that bxt_clk_div need not be exported (Durga) v1: * Rebased on top of intel_dpll_mgr.c (Durga) * Initial version from Ander on top of intel_ddi.c Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Durgadoss R
Rodrigo Vivi
parent
ba88d15352
commit
a277ca7dc0
@ -1460,6 +1460,8 @@ struct bxt_clk_div {
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uint32_t m2_frac;
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bool m2_frac_en;
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uint32_t n;
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int vco;
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};
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/* pre-calculated values for DP linkrates */
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@ -1473,57 +1475,59 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = {
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{432000, 3, 1, 32, 1677722, 1, 1}
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};
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static struct intel_shared_dpll *
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bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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static bool
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bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state, int clock,
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struct bxt_clk_div *clk_div)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_shared_dpll *pll;
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enum intel_dpll_id i;
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struct intel_digital_port *intel_dig_port;
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struct bxt_clk_div clk_div = {0};
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int vco = 0;
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struct dpll best_clock;
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/* Calculate HDMI div */
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/*
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* FIXME: tie the following calculation into
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* i9xx_crtc_compute_clock
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*/
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if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
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DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
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clock, pipe_name(intel_crtc->pipe));
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return false;
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}
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clk_div->p1 = best_clock.p1;
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clk_div->p2 = best_clock.p2;
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WARN_ON(best_clock.m1 != 2);
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clk_div->n = best_clock.n;
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clk_div->m2_int = best_clock.m2 >> 22;
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clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
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clk_div->m2_frac_en = clk_div->m2_frac != 0;
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clk_div->vco = best_clock.vco;
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return true;
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}
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static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
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{
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int i;
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*clk_div = bxt_dp_clk_val[0];
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for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
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if (bxt_dp_clk_val[i].clock == clock) {
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*clk_div = bxt_dp_clk_val[i];
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break;
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}
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}
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clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
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}
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static bool bxt_ddi_set_dpll_hw_state(int clock,
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struct bxt_clk_div *clk_div,
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struct intel_dpll_hw_state *dpll_hw_state)
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{
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int vco = clk_div->vco;
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uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
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uint32_t lanestagger;
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int clock = crtc_state->port_clock;
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if (encoder->type == INTEL_OUTPUT_HDMI) {
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struct dpll best_clock;
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/* Calculate HDMI div */
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/*
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* FIXME: tie the following calculation into
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* i9xx_crtc_compute_clock
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*/
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if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
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DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
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clock, pipe_name(crtc->pipe));
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return NULL;
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}
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clk_div.p1 = best_clock.p1;
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clk_div.p2 = best_clock.p2;
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WARN_ON(best_clock.m1 != 2);
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clk_div.n = best_clock.n;
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clk_div.m2_int = best_clock.m2 >> 22;
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clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
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clk_div.m2_frac_en = clk_div.m2_frac != 0;
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vco = best_clock.vco;
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} else if (encoder->type == INTEL_OUTPUT_DP ||
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encoder->type == INTEL_OUTPUT_EDP ||
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encoder->type == INTEL_OUTPUT_DP_MST) {
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int i;
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clk_div = bxt_dp_clk_val[0];
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for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
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if (bxt_dp_clk_val[i].clock == clock) {
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clk_div = bxt_dp_clk_val[i];
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break;
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}
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}
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vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
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}
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if (vco >= 6200000 && vco <= 6700000) {
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prop_coef = 4;
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@ -1543,12 +1547,9 @@ bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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targ_cnt = 9;
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} else {
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DRM_ERROR("Invalid VCO\n");
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return NULL;
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return false;
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}
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (clock > 270000)
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lanestagger = 0x18;
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else if (clock > 135000)
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@ -1560,33 +1561,68 @@ bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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else
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lanestagger = 0x02;
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crtc_state->dpll_hw_state.ebb0 =
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PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
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crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
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crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
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crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
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dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
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dpll_hw_state->pll0 = clk_div->m2_int;
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dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
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dpll_hw_state->pll2 = clk_div->m2_frac;
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if (clk_div.m2_frac_en)
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crtc_state->dpll_hw_state.pll3 =
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PORT_PLL_M2_FRAC_ENABLE;
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if (clk_div->m2_frac_en)
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dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
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crtc_state->dpll_hw_state.pll6 =
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prop_coef | PORT_PLL_INT_COEFF(int_coef);
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crtc_state->dpll_hw_state.pll6 |=
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PORT_PLL_GAIN_CTL(gain_ctl);
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dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
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dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
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crtc_state->dpll_hw_state.pll8 = targ_cnt;
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dpll_hw_state->pll8 = targ_cnt;
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crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
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dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
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crtc_state->dpll_hw_state.pll10 =
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dpll_hw_state->pll10 =
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PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
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| PORT_PLL_DCO_AMP_OVR_EN_H;
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crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
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dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
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crtc_state->dpll_hw_state.pcsdw12 =
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LANESTAGGER_STRAP_OVRD | lanestagger;
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dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
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return true;
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}
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bool bxt_ddi_dp_set_dpll_hw_state(int clock,
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struct intel_dpll_hw_state *dpll_hw_state)
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{
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struct bxt_clk_div clk_div = {0};
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bxt_ddi_dp_pll_dividers(clock, &clk_div);
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return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
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}
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static struct intel_shared_dpll *
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bxt_get_dpll(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder)
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{
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struct bxt_clk_div clk_div = {0};
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struct intel_dpll_hw_state dpll_hw_state = {0};
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_digital_port *intel_dig_port;
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struct intel_shared_dpll *pll;
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int i, clock = crtc_state->port_clock;
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if (encoder->type == INTEL_OUTPUT_HDMI
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&& !bxt_ddi_hdmi_pll_dividers(crtc, crtc_state,
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clock, &clk_div))
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return false;
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if ((encoder->type == INTEL_OUTPUT_DP ||
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encoder->type == INTEL_OUTPUT_EDP) &&
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!bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
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return false;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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crtc_state->dpll_hw_state = dpll_hw_state;
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if (encoder->type == INTEL_OUTPUT_DP_MST) {
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struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
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@ -160,5 +160,8 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc);
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void intel_shared_dpll_commit(struct drm_atomic_state *state);
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void intel_shared_dpll_init(struct drm_device *dev);
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/* BXT dpll related functions */
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bool bxt_ddi_dp_set_dpll_hw_state(int clock,
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struct intel_dpll_hw_state *dpll_hw_state);
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#endif /* _INTEL_DPLL_MGR_H_ */
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