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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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staging: dgnc: re-arrange functions for removing
Re-arrange the functions for removing forward declarations in dgnc_cls.c file. Signed-off-by: Daeseok Youn <daeseok.youn@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Daeseok Youn
Greg Kroah-Hartman
parent
c23b48e0ed
commit
a2237a2d60
@ -26,56 +26,6 @@
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#include "dgnc_cls.h"
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#include "dgnc_tty.h"
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static inline void cls_parse_isr(struct dgnc_board *brd, uint port);
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static inline void cls_clear_break(struct channel_t *ch, int force);
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static inline void cls_set_cts_flow_control(struct channel_t *ch);
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static inline void cls_set_rts_flow_control(struct channel_t *ch);
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static inline void cls_set_ixon_flow_control(struct channel_t *ch);
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static inline void cls_set_ixoff_flow_control(struct channel_t *ch);
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static inline void cls_set_no_output_flow_control(struct channel_t *ch);
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static inline void cls_set_no_input_flow_control(struct channel_t *ch);
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static void cls_parse_modem(struct channel_t *ch, unsigned char signals);
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static void cls_tasklet(unsigned long data);
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static void cls_vpd(struct dgnc_board *brd);
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static void cls_uart_init(struct channel_t *ch);
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static void cls_uart_off(struct channel_t *ch);
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static int cls_drain(struct tty_struct *tty, uint seconds);
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static void cls_param(struct tty_struct *tty);
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static void cls_assert_modem_signals(struct channel_t *ch);
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static void cls_flush_uart_write(struct channel_t *ch);
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static void cls_flush_uart_read(struct channel_t *ch);
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static void cls_disable_receiver(struct channel_t *ch);
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static void cls_enable_receiver(struct channel_t *ch);
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static void cls_send_break(struct channel_t *ch, int msecs);
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static void cls_send_start_character(struct channel_t *ch);
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static void cls_send_stop_character(struct channel_t *ch);
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static void cls_copy_data_from_uart_to_queue(struct channel_t *ch);
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static void cls_copy_data_from_queue_to_uart(struct channel_t *ch);
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static uint cls_get_uart_bytes_left(struct channel_t *ch);
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static void cls_send_immediate_char(struct channel_t *ch, unsigned char);
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static irqreturn_t cls_intr(int irq, void *voidbrd);
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struct board_ops dgnc_cls_ops = {
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.tasklet = cls_tasklet,
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.intr = cls_intr,
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.uart_init = cls_uart_init,
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.uart_off = cls_uart_off,
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.drain = cls_drain,
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.param = cls_param,
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.vpd = cls_vpd,
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.assert_modem_signals = cls_assert_modem_signals,
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.flush_uart_write = cls_flush_uart_write,
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.flush_uart_read = cls_flush_uart_read,
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.disable_receiver = cls_disable_receiver,
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.enable_receiver = cls_enable_receiver,
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.send_break = cls_send_break,
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.send_start_character = cls_send_start_character,
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.send_stop_character = cls_send_stop_character,
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.copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
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.get_uart_bytes_left = cls_get_uart_bytes_left,
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.send_immediate_char = cls_send_immediate_char
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};
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static inline void cls_set_cts_flow_control(struct channel_t *ch)
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{
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unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
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@ -357,6 +307,253 @@ static inline void cls_clear_break(struct channel_t *ch, int force)
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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}
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static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
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{
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int qleft = 0;
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unsigned char linestatus = 0;
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unsigned char error_mask = 0;
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ushort head;
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ushort tail;
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unsigned long flags;
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
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return;
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spin_lock_irqsave(&ch->ch_lock, flags);
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/* cache head and tail of queue */
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head = ch->ch_r_head;
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tail = ch->ch_r_tail;
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/* Store how much space we have left in the queue */
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qleft = tail - head - 1;
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if (qleft < 0)
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qleft += RQUEUEMASK + 1;
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/*
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* Create a mask to determine whether we should
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* insert the character (if any) into our queue.
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*/
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if (ch->ch_c_iflag & IGNBRK)
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error_mask |= UART_LSR_BI;
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while (1) {
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linestatus = readb(&ch->ch_cls_uart->lsr);
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if (!(linestatus & (UART_LSR_DR)))
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break;
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/*
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* Discard character if we are ignoring the error mask.
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*/
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if (linestatus & error_mask) {
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linestatus = 0;
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readb(&ch->ch_cls_uart->txrx);
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continue;
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}
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/*
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* If our queue is full, we have no choice but to drop some
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* data. The assumption is that HWFLOW or SWFLOW should have
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* stopped things way way before we got to this point.
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*
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* I decided that I wanted to ditch the oldest data first,
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* I hope thats okay with everyone? Yes? Good.
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*/
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while (qleft < 1) {
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tail = (tail + 1) & RQUEUEMASK;
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ch->ch_r_tail = tail;
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ch->ch_err_overrun++;
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qleft++;
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}
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ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
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| UART_LSR_FE);
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ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
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qleft--;
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if (ch->ch_equeue[head] & UART_LSR_PE)
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ch->ch_err_parity++;
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if (ch->ch_equeue[head] & UART_LSR_BI)
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ch->ch_err_break++;
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if (ch->ch_equeue[head] & UART_LSR_FE)
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ch->ch_err_frame++;
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/* Add to, and flip head if needed */
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head = (head + 1) & RQUEUEMASK;
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ch->ch_rxcount++;
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}
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/*
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* Write new final heads to channel structure.
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*/
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ch->ch_r_head = head & RQUEUEMASK;
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ch->ch_e_head = head & EQUEUEMASK;
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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}
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/* Make the UART raise any of the output signals we want up */
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static void cls_assert_modem_signals(struct channel_t *ch)
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{
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unsigned char out;
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
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return;
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out = ch->ch_mostat;
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if (ch->ch_flags & CH_LOOPBACK)
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out |= UART_MCR_LOOP;
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writeb(out, &ch->ch_cls_uart->mcr);
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/* Give time for the UART to actually drop the signals */
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udelay(10);
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}
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static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
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{
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ushort head;
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ushort tail;
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int n;
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int qlen;
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uint len_written = 0;
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unsigned long flags;
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
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return;
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spin_lock_irqsave(&ch->ch_lock, flags);
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/* No data to write to the UART */
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if (ch->ch_w_tail == ch->ch_w_head)
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goto exit_unlock;
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/* If port is "stopped", don't send any data to the UART */
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if ((ch->ch_flags & CH_FORCED_STOP) ||
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(ch->ch_flags & CH_BREAK_SENDING))
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goto exit_unlock;
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if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
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goto exit_unlock;
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n = 32;
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/* cache head and tail of queue */
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head = ch->ch_w_head & WQUEUEMASK;
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tail = ch->ch_w_tail & WQUEUEMASK;
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qlen = (head - tail) & WQUEUEMASK;
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/* Find minimum of the FIFO space, versus queue length */
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n = min(n, qlen);
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while (n > 0) {
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/*
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* If RTS Toggle mode is on, turn on RTS now if not already set,
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* and make sure we get an event when the data transfer has
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* completed.
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*/
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if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
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if (!(ch->ch_mostat & UART_MCR_RTS)) {
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ch->ch_mostat |= (UART_MCR_RTS);
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cls_assert_modem_signals(ch);
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}
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ch->ch_tun.un_flags |= (UN_EMPTY);
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}
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/*
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* If DTR Toggle mode is on, turn on DTR now if not already set,
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* and make sure we get an event when the data transfer has
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* completed.
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*/
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if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
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if (!(ch->ch_mostat & UART_MCR_DTR)) {
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ch->ch_mostat |= (UART_MCR_DTR);
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cls_assert_modem_signals(ch);
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}
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ch->ch_tun.un_flags |= (UN_EMPTY);
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}
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writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
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ch->ch_w_tail++;
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ch->ch_w_tail &= WQUEUEMASK;
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ch->ch_txcount++;
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len_written++;
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n--;
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}
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if (len_written > 0)
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ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
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exit_unlock:
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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}
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static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
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{
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unsigned char msignals = signals;
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unsigned long flags;
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
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return;
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/*
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* Do altpin switching. Altpin switches DCD and DSR.
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* This prolly breaks DSRPACE, so we should be more clever here.
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*/
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spin_lock_irqsave(&ch->ch_lock, flags);
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if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
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unsigned char mswap = signals;
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if (mswap & UART_MSR_DDCD) {
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msignals &= ~UART_MSR_DDCD;
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msignals |= UART_MSR_DDSR;
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}
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if (mswap & UART_MSR_DDSR) {
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msignals &= ~UART_MSR_DDSR;
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msignals |= UART_MSR_DDCD;
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}
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if (mswap & UART_MSR_DCD) {
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msignals &= ~UART_MSR_DCD;
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msignals |= UART_MSR_DSR;
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}
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if (mswap & UART_MSR_DSR) {
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msignals &= ~UART_MSR_DSR;
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msignals |= UART_MSR_DCD;
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}
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}
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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/*
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* Scrub off lower bits. They signify delta's, which I don't
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* care about
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*/
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signals &= 0xf0;
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spin_lock_irqsave(&ch->ch_lock, flags);
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if (msignals & UART_MSR_DCD)
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ch->ch_mistat |= UART_MSR_DCD;
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else
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ch->ch_mistat &= ~UART_MSR_DCD;
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if (msignals & UART_MSR_DSR)
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ch->ch_mistat |= UART_MSR_DSR;
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else
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ch->ch_mistat &= ~UART_MSR_DSR;
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if (msignals & UART_MSR_RI)
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ch->ch_mistat |= UART_MSR_RI;
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else
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ch->ch_mistat &= ~UART_MSR_RI;
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if (msignals & UART_MSR_CTS)
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ch->ch_mistat |= UART_MSR_CTS;
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else
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ch->ch_mistat &= ~UART_MSR_CTS;
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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}
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/* Parse the ISR register for the specific port */
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static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
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{
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@ -419,6 +616,39 @@ static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
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}
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}
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/* Channel lock MUST be held before calling this function! */
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static void cls_flush_uart_write(struct channel_t *ch)
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{
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
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return;
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writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
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&ch->ch_cls_uart->isr_fcr);
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usleep_range(10, 20);
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ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
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}
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/* Channel lock MUST be held before calling this function! */
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static void cls_flush_uart_read(struct channel_t *ch)
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{
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
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return;
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/*
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* For complete POSIX compatibility, we should be purging the
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* read FIFO in the UART here.
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*
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* However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
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* incorrectly flushes write data as well as just basically trashing the
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* FIFO.
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*
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* Presumably, this is a bug in this UART.
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*/
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udelay(10);
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}
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/*
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* cls_param()
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* Send any/all changes to the line to the UART.
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@ -804,93 +1034,6 @@ static void cls_enable_receiver(struct channel_t *ch)
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writeb(tmp, &ch->ch_cls_uart->ier);
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}
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static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
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{
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int qleft = 0;
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unsigned char linestatus = 0;
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unsigned char error_mask = 0;
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ushort head;
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ushort tail;
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unsigned long flags;
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
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return;
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spin_lock_irqsave(&ch->ch_lock, flags);
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/* cache head and tail of queue */
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head = ch->ch_r_head;
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tail = ch->ch_r_tail;
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/* Store how much space we have left in the queue */
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qleft = tail - head - 1;
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if (qleft < 0)
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qleft += RQUEUEMASK + 1;
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/*
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* Create a mask to determine whether we should
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* insert the character (if any) into our queue.
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*/
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if (ch->ch_c_iflag & IGNBRK)
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error_mask |= UART_LSR_BI;
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while (1) {
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linestatus = readb(&ch->ch_cls_uart->lsr);
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if (!(linestatus & (UART_LSR_DR)))
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break;
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/*
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* Discard character if we are ignoring the error mask.
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*/
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if (linestatus & error_mask) {
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linestatus = 0;
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readb(&ch->ch_cls_uart->txrx);
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continue;
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}
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/*
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* If our queue is full, we have no choice but to drop some
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* data. The assumption is that HWFLOW or SWFLOW should have
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* stopped things way way before we got to this point.
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*
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* I decided that I wanted to ditch the oldest data first,
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* I hope thats okay with everyone? Yes? Good.
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*/
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while (qleft < 1) {
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tail = (tail + 1) & RQUEUEMASK;
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ch->ch_r_tail = tail;
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ch->ch_err_overrun++;
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qleft++;
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}
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ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
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| UART_LSR_FE);
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ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
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qleft--;
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if (ch->ch_equeue[head] & UART_LSR_PE)
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ch->ch_err_parity++;
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if (ch->ch_equeue[head] & UART_LSR_BI)
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ch->ch_err_break++;
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if (ch->ch_equeue[head] & UART_LSR_FE)
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ch->ch_err_frame++;
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/* Add to, and flip head if needed */
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head = (head + 1) & RQUEUEMASK;
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ch->ch_rxcount++;
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}
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/*
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* Write new final heads to channel structure.
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*/
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ch->ch_r_head = head & RQUEUEMASK;
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ch->ch_e_head = head & EQUEUEMASK;
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spin_unlock_irqrestore(&ch->ch_lock, flags);
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}
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/*
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* This function basically goes to sleep for secs, or until
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* it gets signalled that the port has fully drained.
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@ -926,199 +1069,6 @@ static int cls_drain(struct tty_struct *tty, uint seconds)
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((un->un_flags & UN_EMPTY) == 0));
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}
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|
||||
/* Channel lock MUST be held before calling this function! */
|
||||
static void cls_flush_uart_write(struct channel_t *ch)
|
||||
{
|
||||
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
|
||||
return;
|
||||
|
||||
writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
|
||||
&ch->ch_cls_uart->isr_fcr);
|
||||
usleep_range(10, 20);
|
||||
|
||||
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
|
||||
}
|
||||
|
||||
/* Channel lock MUST be held before calling this function! */
|
||||
static void cls_flush_uart_read(struct channel_t *ch)
|
||||
{
|
||||
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
|
||||
return;
|
||||
|
||||
/*
|
||||
* For complete POSIX compatibility, we should be purging the
|
||||
* read FIFO in the UART here.
|
||||
*
|
||||
* However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
|
||||
* incorrectly flushes write data as well as just basically trashing the
|
||||
* FIFO.
|
||||
*
|
||||
* Presumably, this is a bug in this UART.
|
||||
*/
|
||||
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
|
||||
{
|
||||
ushort head;
|
||||
ushort tail;
|
||||
int n;
|
||||
int qlen;
|
||||
uint len_written = 0;
|
||||
unsigned long flags;
|
||||
|
||||
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&ch->ch_lock, flags);
|
||||
|
||||
/* No data to write to the UART */
|
||||
if (ch->ch_w_tail == ch->ch_w_head)
|
||||
goto exit_unlock;
|
||||
|
||||
/* If port is "stopped", don't send any data to the UART */
|
||||
if ((ch->ch_flags & CH_FORCED_STOP) ||
|
||||
(ch->ch_flags & CH_BREAK_SENDING))
|
||||
goto exit_unlock;
|
||||
|
||||
if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
|
||||
goto exit_unlock;
|
||||
|
||||
n = 32;
|
||||
|
||||
/* cache head and tail of queue */
|
||||
head = ch->ch_w_head & WQUEUEMASK;
|
||||
tail = ch->ch_w_tail & WQUEUEMASK;
|
||||
qlen = (head - tail) & WQUEUEMASK;
|
||||
|
||||
/* Find minimum of the FIFO space, versus queue length */
|
||||
n = min(n, qlen);
|
||||
|
||||
while (n > 0) {
|
||||
/*
|
||||
* If RTS Toggle mode is on, turn on RTS now if not already set,
|
||||
* and make sure we get an event when the data transfer has
|
||||
* completed.
|
||||
*/
|
||||
if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
|
||||
if (!(ch->ch_mostat & UART_MCR_RTS)) {
|
||||
ch->ch_mostat |= (UART_MCR_RTS);
|
||||
cls_assert_modem_signals(ch);
|
||||
}
|
||||
ch->ch_tun.un_flags |= (UN_EMPTY);
|
||||
}
|
||||
|
||||
/*
|
||||
* If DTR Toggle mode is on, turn on DTR now if not already set,
|
||||
* and make sure we get an event when the data transfer has
|
||||
* completed.
|
||||
*/
|
||||
if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
|
||||
if (!(ch->ch_mostat & UART_MCR_DTR)) {
|
||||
ch->ch_mostat |= (UART_MCR_DTR);
|
||||
cls_assert_modem_signals(ch);
|
||||
}
|
||||
ch->ch_tun.un_flags |= (UN_EMPTY);
|
||||
}
|
||||
writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
|
||||
ch->ch_w_tail++;
|
||||
ch->ch_w_tail &= WQUEUEMASK;
|
||||
ch->ch_txcount++;
|
||||
len_written++;
|
||||
n--;
|
||||
}
|
||||
|
||||
if (len_written > 0)
|
||||
ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
|
||||
|
||||
exit_unlock:
|
||||
spin_unlock_irqrestore(&ch->ch_lock, flags);
|
||||
}
|
||||
|
||||
static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
|
||||
{
|
||||
unsigned char msignals = signals;
|
||||
unsigned long flags;
|
||||
|
||||
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Do altpin switching. Altpin switches DCD and DSR.
|
||||
* This prolly breaks DSRPACE, so we should be more clever here.
|
||||
*/
|
||||
spin_lock_irqsave(&ch->ch_lock, flags);
|
||||
if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
|
||||
unsigned char mswap = signals;
|
||||
|
||||
if (mswap & UART_MSR_DDCD) {
|
||||
msignals &= ~UART_MSR_DDCD;
|
||||
msignals |= UART_MSR_DDSR;
|
||||
}
|
||||
if (mswap & UART_MSR_DDSR) {
|
||||
msignals &= ~UART_MSR_DDSR;
|
||||
msignals |= UART_MSR_DDCD;
|
||||
}
|
||||
if (mswap & UART_MSR_DCD) {
|
||||
msignals &= ~UART_MSR_DCD;
|
||||
msignals |= UART_MSR_DSR;
|
||||
}
|
||||
if (mswap & UART_MSR_DSR) {
|
||||
msignals &= ~UART_MSR_DSR;
|
||||
msignals |= UART_MSR_DCD;
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&ch->ch_lock, flags);
|
||||
|
||||
/*
|
||||
* Scrub off lower bits. They signify delta's, which I don't
|
||||
* care about
|
||||
*/
|
||||
signals &= 0xf0;
|
||||
|
||||
spin_lock_irqsave(&ch->ch_lock, flags);
|
||||
if (msignals & UART_MSR_DCD)
|
||||
ch->ch_mistat |= UART_MSR_DCD;
|
||||
else
|
||||
ch->ch_mistat &= ~UART_MSR_DCD;
|
||||
|
||||
if (msignals & UART_MSR_DSR)
|
||||
ch->ch_mistat |= UART_MSR_DSR;
|
||||
else
|
||||
ch->ch_mistat &= ~UART_MSR_DSR;
|
||||
|
||||
if (msignals & UART_MSR_RI)
|
||||
ch->ch_mistat |= UART_MSR_RI;
|
||||
else
|
||||
ch->ch_mistat &= ~UART_MSR_RI;
|
||||
|
||||
if (msignals & UART_MSR_CTS)
|
||||
ch->ch_mistat |= UART_MSR_CTS;
|
||||
else
|
||||
ch->ch_mistat &= ~UART_MSR_CTS;
|
||||
spin_unlock_irqrestore(&ch->ch_lock, flags);
|
||||
}
|
||||
|
||||
/* Make the UART raise any of the output signals we want up */
|
||||
static void cls_assert_modem_signals(struct channel_t *ch)
|
||||
{
|
||||
unsigned char out;
|
||||
|
||||
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
|
||||
return;
|
||||
|
||||
out = ch->ch_mostat;
|
||||
|
||||
if (ch->ch_flags & CH_LOOPBACK)
|
||||
out |= UART_MCR_LOOP;
|
||||
|
||||
writeb(out, &ch->ch_cls_uart->mcr);
|
||||
|
||||
/* Give time for the UART to actually drop the signals */
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
static void cls_send_start_character(struct channel_t *ch)
|
||||
{
|
||||
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
|
||||
@ -1298,3 +1248,24 @@ static void cls_vpd(struct dgnc_board *brd)
|
||||
|
||||
iounmap(re_map_vpdbase);
|
||||
}
|
||||
|
||||
struct board_ops dgnc_cls_ops = {
|
||||
.tasklet = cls_tasklet,
|
||||
.intr = cls_intr,
|
||||
.uart_init = cls_uart_init,
|
||||
.uart_off = cls_uart_off,
|
||||
.drain = cls_drain,
|
||||
.param = cls_param,
|
||||
.vpd = cls_vpd,
|
||||
.assert_modem_signals = cls_assert_modem_signals,
|
||||
.flush_uart_write = cls_flush_uart_write,
|
||||
.flush_uart_read = cls_flush_uart_read,
|
||||
.disable_receiver = cls_disable_receiver,
|
||||
.enable_receiver = cls_enable_receiver,
|
||||
.send_break = cls_send_break,
|
||||
.send_start_character = cls_send_start_character,
|
||||
.send_stop_character = cls_send_stop_character,
|
||||
.copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
|
||||
.get_uart_bytes_left = cls_get_uart_bytes_left,
|
||||
.send_immediate_char = cls_send_immediate_char
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user