mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 16:20:53 +07:00
Timer fixes for omaps via Jon Hunter <jon-hunter@ti.com>:
Several fixes for the OMAP DMTIMER driver including ... 1. Adding workaround for OMAP3+ errata i103/i767 2. Fixing posted mode support 3. Spurious interrupts when using match interrupt 4. HWMOD fixes for timers 5. Unnecessary restoration of read-only registers 6. Adds function for disabling timer interrupts 7. Fixing timer1 reset for OMAP1 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQosWdAAoJEBvUPslcq6VzZ/YP/2VaVPE9qimeBT6J0b52KE74 uNtR9dyBAO/xFjhUAZBfDud9R2sM/SZl98CNBmUZ2/PoFAgreeiU8SxNk9DqilS7 B+3XxLz/YR7rcxBb7irHSGh+zt1CBZBI61f33iWBA+58jH7YYitZx9FGVB7C8Zk7 eLFVtMwGtyZwXqr0ZPzJJUWeZSXJ5AwUvKDrdoVmqltO1MPEroSxN4LDVWWaGGgT ehV0e+DEVL+RpdoOHBvbphqwLKTeO0PR2LNrex5ocb2EQ34ugKkfNkrFxXGQM2Lw qLIyfgspi/eWjDgW4cL+T8uLZw0UXJsvTHNAhRypl0voLjDW46UNzWWuOsOGJJH1 wD3H2qtGihewaU1umIGLKVuX+QfrohrnRMfT8J1hMCD6iQTRaSgeiEuO28+ARcrV TuSEdBAc0mMkR62ahQa/PEov/MlvHhNsfBwnTidDfejGjdNvNCpIpJj5rjluTbnk nNSndIV3QsoI+fOdlxwFIpzPLqGlpyJvrf9hlnm3RZm5tCPU4Xw34ATcJ8YY0zu6 WdveMEZdRiw9EO00Qh8KiN4EImrfrwMHl1WXSX0PHVXD+kSdcJZTOGaYGQaDy+L+ 3n814KGmNwWM88pqm18nHkzvRgWflC2V/Rx895uVz2O1oK/pKVL7+rPuhfSs1w8w 0ySj7w7xsM2CsfSasu9l =xPPb -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.8/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers From Tony Lindgren <tony@atomide.com>: Timer fixes for omaps via Jon Hunter <jon-hunter@ti.com>: Several fixes for the OMAP DMTIMER driver including ... 1. Adding workaround for OMAP3+ errata i103/i767 2. Fixing posted mode support 3. Spurious interrupts when using match interrupt 4. HWMOD fixes for timers 5. Unnecessary restoration of read-only registers 6. Adds function for disabling timer interrupts 7. Fixing timer1 reset for OMAP1 * tag 'omap-for-v3.8/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP: Remove __omap_dm_timer_set_source function ARM: OMAP: Remove unnecessary call to clk_get() ARM: OMAP: Add dmtimer interrupt disable function ARM: OMAP: Fix spurious interrupts when using timer match feature ARM: OMAP: Don't restore DMTIMER interrupt status register ARM: OMAP: Don't restore of DMTIMER TISTAT register ARM: OMAP: Fix dmtimer reset for timer1 ARM: OMAP2+: Don't use __omap_dm_timer_reset() ARM: OMAP2/3: Define HWMOD software reset status for DMTIMERs ARM: OMAP3: Correct HWMOD DMTIMER SYSC register declarations ARM: OMAP: Fix timer posted mode support ARM: OMAP3+: Implement timer workaround for errata i103 and i767 ARM: OMAP: Add DMTIMER definitions for posted mode Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
a19e233779
@ -58,8 +58,9 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.clockact = CLOCKACT_TEST_ICLK,
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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@ -268,6 +269,7 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
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},
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.dev_attr = &capability_alwon_dev_attr,
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer2 */
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@ -286,6 +288,7 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
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},
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},
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer3 */
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@ -304,6 +307,7 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
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},
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},
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer4 */
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@ -322,6 +326,7 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
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},
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},
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer5 */
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@ -341,6 +346,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
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},
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.dev_attr = &capability_dsp_dev_attr,
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer6 */
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@ -360,6 +366,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
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},
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.dev_attr = &capability_dsp_dev_attr,
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer7 */
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@ -379,6 +386,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
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},
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.dev_attr = &capability_dsp_dev_attr,
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer8 */
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@ -398,6 +406,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
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},
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.dev_attr = &capability_dsp_dev_attr,
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer9 */
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@ -417,6 +426,7 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
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},
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.dev_attr = &capability_pwm_dev_attr,
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer10 */
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@ -436,6 +446,7 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
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},
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.dev_attr = &capability_pwm_dev_attr,
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer11 */
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@ -455,6 +466,7 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
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},
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.dev_attr = &capability_pwm_dev_attr,
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer12 */
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@ -474,6 +486,7 @@ struct omap_hwmod omap2xxx_timer12_hwmod = {
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},
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.dev_attr = &capability_pwm_dev_attr,
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.class = &omap2xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* wd_timer2 */
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@ -153,29 +153,16 @@ static struct omap_hwmod omap3xxx_debugss_hwmod = {
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};
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/* timer class */
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static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
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.name = "timer",
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.sysc = &omap3xxx_timer_1ms_sysc,
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};
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static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
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SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.clockact = CLOCKACT_TEST_ICLK,
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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@ -224,7 +211,8 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
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},
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},
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.dev_attr = &capability_alwon_dev_attr,
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.class = &omap3xxx_timer_1ms_hwmod_class,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer2 */
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@ -241,7 +229,8 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
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.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
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},
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},
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.class = &omap3xxx_timer_1ms_hwmod_class,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer3 */
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@ -259,6 +248,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
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},
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},
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer4 */
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@ -276,6 +266,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
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},
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},
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer5 */
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@ -294,6 +285,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
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},
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.dev_attr = &capability_dsp_dev_attr,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer6 */
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@ -312,6 +304,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
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},
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.dev_attr = &capability_dsp_dev_attr,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer7 */
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@ -330,6 +323,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
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},
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.dev_attr = &capability_dsp_dev_attr,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer8 */
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@ -348,6 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
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},
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.dev_attr = &capability_dsp_pwm_dev_attr,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer9 */
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@ -366,6 +361,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
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},
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.dev_attr = &capability_pwm_dev_attr,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer10 */
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@ -383,7 +379,8 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
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},
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},
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.dev_attr = &capability_pwm_dev_attr,
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.class = &omap3xxx_timer_1ms_hwmod_class,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer11 */
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@ -402,6 +399,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
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},
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.dev_attr = &capability_pwm_dev_attr,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer12 */
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@ -425,6 +423,7 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
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},
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.dev_attr = &capability_secure_dev_attr,
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/*
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@ -3067,6 +3067,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
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SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.clockact = CLOCKACT_TEST_ICLK,
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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@ -3120,6 +3121,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
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.name = "timer1",
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.class = &omap44xx_timer_1ms_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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.mpu_irqs = omap44xx_timer1_irqs,
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.main_clk = "timer1_fck",
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.prcm = {
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@ -3142,6 +3144,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
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.name = "timer2",
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.class = &omap44xx_timer_1ms_hwmod_class,
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.clkdm_name = "l4_per_clkdm",
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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.mpu_irqs = omap44xx_timer2_irqs,
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.main_clk = "timer2_fck",
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.prcm = {
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@ -3316,6 +3319,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
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.name = "timer10",
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.class = &omap44xx_timer_1ms_hwmod_class,
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.clkdm_name = "l4_per_clkdm",
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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.mpu_irqs = omap44xx_timer10_irqs,
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.main_clk = "timer10_fck",
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.prcm = {
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@ -108,7 +108,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
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0xffffffff - cycles, 1);
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0xffffffff - cycles, OMAP_TIMER_POSTED);
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return 0;
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}
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@ -118,7 +118,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
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{
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u32 period;
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__omap_dm_timer_stop(&clkev, 1, clkev.rate);
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__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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@ -126,10 +126,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
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period -= 1;
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/* Looks like we need to first set the load value separately */
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__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
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0xffffffff - period, 1);
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0xffffffff - period, OMAP_TIMER_POSTED);
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__omap_dm_timer_load_start(&clkev,
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OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
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0xffffffff - period, 1);
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0xffffffff - period, OMAP_TIMER_POSTED);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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@ -222,10 +222,24 @@ void __init omap_dmtimer_init(void)
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}
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}
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/**
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* omap_dm_timer_get_errata - get errata flags for a timer
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*
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* Get the timer errata flags that are specific to the OMAP device being used.
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*/
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u32 __init omap_dm_timer_get_errata(void)
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{
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if (cpu_is_omap24xx())
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return 0;
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return OMAP_TIMER_ERRATA_I103_I767;
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}
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static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
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int gptimer_id,
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const char *fck_source,
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const char *property)
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const char *property,
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int posted)
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{
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char name[10]; /* 10 = sizeof("gptXX_Xck0") */
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const char *oh_name;
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@ -260,9 +274,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
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oh_name = name;
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}
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omap_hwmod_setup_one(oh_name);
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oh = omap_hwmod_lookup(oh_name);
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if (!oh)
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return -ENODEV;
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@ -292,8 +304,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
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if (IS_ERR(timer->fclk))
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return -ENODEV;
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omap_hwmod_enable(oh);
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/* FIXME: Need to remove hard-coded test on timer ID */
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if (gptimer_id != 12) {
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struct clk *src;
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@ -302,19 +312,26 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
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if (IS_ERR(src)) {
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res = -EINVAL;
|
||||
} else {
|
||||
res = __omap_dm_timer_set_source(timer->fclk, src);
|
||||
res = clk_set_parent(timer->fclk, src);
|
||||
if (IS_ERR_VALUE(res))
|
||||
pr_warn("%s: %s cannot set source\n",
|
||||
__func__, oh->name);
|
||||
clk_put(src);
|
||||
}
|
||||
}
|
||||
|
||||
omap_hwmod_setup_one(oh_name);
|
||||
omap_hwmod_enable(oh);
|
||||
__omap_dm_timer_init_regs(timer);
|
||||
__omap_dm_timer_reset(timer, 1, 1);
|
||||
timer->posted = 1;
|
||||
|
||||
if (posted)
|
||||
__omap_dm_timer_enable_posted(timer);
|
||||
|
||||
/* Check that the intended posted configuration matches the actual */
|
||||
if (posted != timer->posted)
|
||||
return -EINVAL;
|
||||
|
||||
timer->rate = clk_get_rate(timer->fclk);
|
||||
|
||||
timer->reserved = 1;
|
||||
|
||||
return res;
|
||||
@ -326,7 +343,17 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
|
||||
{
|
||||
int res;
|
||||
|
||||
res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property);
|
||||
clkev.errata = omap_dm_timer_get_errata();
|
||||
|
||||
/*
|
||||
* For clock-event timers we never read the timer counter and
|
||||
* so we are not impacted by errata i103 and i767. Therefore,
|
||||
* we can safely ignore this errata for clock-event timers.
|
||||
*/
|
||||
__omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
|
||||
|
||||
res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
|
||||
OMAP_TIMER_POSTED);
|
||||
BUG_ON(res);
|
||||
|
||||
omap2_gp_timer_irq.dev_id = &clkev;
|
||||
@ -359,7 +386,8 @@ static bool use_gptimer_clksrc;
|
||||
*/
|
||||
static cycle_t clocksource_read_cycles(struct clocksource *cs)
|
||||
{
|
||||
return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
|
||||
return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
|
||||
OMAP_TIMER_NONPOSTED);
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_gpt = {
|
||||
@ -373,7 +401,8 @@ static struct clocksource clocksource_gpt = {
|
||||
static u32 notrace dmtimer_read_sched_clock(void)
|
||||
{
|
||||
if (clksrc.reserved)
|
||||
return __omap_dm_timer_read_counter(&clksrc, 1);
|
||||
return __omap_dm_timer_read_counter(&clksrc,
|
||||
OMAP_TIMER_NONPOSTED);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -451,11 +480,15 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
|
||||
{
|
||||
int res;
|
||||
|
||||
res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL);
|
||||
clksrc.errata = omap_dm_timer_get_errata();
|
||||
|
||||
res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
|
||||
OMAP_TIMER_NONPOSTED);
|
||||
BUG_ON(res);
|
||||
|
||||
__omap_dm_timer_load_start(&clksrc,
|
||||
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
|
||||
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
|
||||
OMAP_TIMER_NONPOSTED);
|
||||
setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
|
||||
|
||||
if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
|
||||
@ -693,6 +726,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
|
||||
if (timer_dev_attr)
|
||||
pdata->timer_capability = timer_dev_attr->timer_capability;
|
||||
|
||||
pdata->timer_errata = omap_dm_timer_get_errata();
|
||||
pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
|
||||
|
||||
pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
|
||||
|
||||
@ -35,6 +35,7 @@
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/device.h>
|
||||
@ -83,10 +84,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
|
||||
|
||||
static void omap_timer_restore_context(struct omap_dm_timer *timer)
|
||||
{
|
||||
if (timer->revision == 1)
|
||||
__raw_writel(timer->context.tistat, timer->sys_stat);
|
||||
|
||||
__raw_writel(timer->context.tisr, timer->irq_stat);
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
|
||||
timer->context.twer);
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
|
||||
@ -121,21 +118,13 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
|
||||
|
||||
static void omap_dm_timer_reset(struct omap_dm_timer *timer)
|
||||
{
|
||||
omap_dm_timer_enable(timer);
|
||||
if (timer->pdev->id != 1) {
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
|
||||
omap_dm_timer_wait_for_reset(timer);
|
||||
}
|
||||
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
|
||||
omap_dm_timer_wait_for_reset(timer);
|
||||
__omap_dm_timer_reset(timer, 0, 0);
|
||||
omap_dm_timer_disable(timer);
|
||||
timer->posted = 1;
|
||||
}
|
||||
|
||||
int omap_dm_timer_prepare(struct omap_dm_timer *timer)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* FIXME: OMAP1 devices do not use the clock framework for dmtimers so
|
||||
* do not call clk_get() for these devices.
|
||||
@ -149,13 +138,15 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
|
||||
}
|
||||
}
|
||||
|
||||
omap_dm_timer_enable(timer);
|
||||
|
||||
if (timer->capability & OMAP_TIMER_NEEDS_RESET)
|
||||
omap_dm_timer_reset(timer);
|
||||
|
||||
ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
|
||||
__omap_dm_timer_enable_posted(timer);
|
||||
omap_dm_timer_disable(timer);
|
||||
|
||||
timer->posted = 1;
|
||||
return ret;
|
||||
return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
|
||||
}
|
||||
|
||||
static inline u32 omap_dm_timer_reserved_systimer(int id)
|
||||
@ -449,7 +440,6 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
|
||||
*/
|
||||
timer->context.tclr =
|
||||
omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
||||
timer->context.tisr = __raw_readl(timer->irq_stat);
|
||||
omap_dm_timer_disable(timer);
|
||||
return 0;
|
||||
}
|
||||
@ -459,7 +449,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
||||
{
|
||||
int ret;
|
||||
char *parent_name = NULL;
|
||||
struct clk *fclk, *parent;
|
||||
struct clk *parent;
|
||||
struct dmtimer_platform_data *pdata;
|
||||
|
||||
if (unlikely(!timer))
|
||||
@ -478,11 +468,8 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
||||
if (pdata && pdata->set_timer_src)
|
||||
return pdata->set_timer_src(timer->pdev, source);
|
||||
|
||||
fclk = clk_get(&timer->pdev->dev, "fck");
|
||||
if (IS_ERR_OR_NULL(fclk)) {
|
||||
pr_err("%s: fck not found\n", __func__);
|
||||
if (!timer->fclk)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (source) {
|
||||
case OMAP_TIMER_SRC_SYS_CLK:
|
||||
@ -501,18 +488,15 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
||||
parent = clk_get(&timer->pdev->dev, parent_name);
|
||||
if (IS_ERR_OR_NULL(parent)) {
|
||||
pr_err("%s: %s not found\n", __func__, parent_name);
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = clk_set_parent(fclk, parent);
|
||||
ret = clk_set_parent(timer->fclk, parent);
|
||||
if (IS_ERR_VALUE(ret))
|
||||
pr_err("%s: failed to set %s as parent\n", __func__,
|
||||
parent_name);
|
||||
|
||||
clk_put(parent);
|
||||
out:
|
||||
clk_put(fclk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -595,8 +579,8 @@ int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
|
||||
l |= OMAP_TIMER_CTRL_CE;
|
||||
else
|
||||
l &= ~OMAP_TIMER_CTRL_CE;
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
||||
|
||||
/* Save the context */
|
||||
timer->context.tclr = l;
|
||||
@ -672,6 +656,37 @@ int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
|
||||
|
||||
/**
|
||||
* omap_dm_timer_set_int_disable - disable timer interrupts
|
||||
* @timer: pointer to timer handle
|
||||
* @mask: bit mask of interrupts to be disabled
|
||||
*
|
||||
* Disables the specified timer interrupts for a timer.
|
||||
*/
|
||||
int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
|
||||
{
|
||||
u32 l = mask;
|
||||
|
||||
if (unlikely(!timer))
|
||||
return -EINVAL;
|
||||
|
||||
omap_dm_timer_enable(timer);
|
||||
|
||||
if (timer->revision == 1)
|
||||
l = __raw_readl(timer->irq_ena) & ~mask;
|
||||
|
||||
__raw_writel(l, timer->irq_dis);
|
||||
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
|
||||
|
||||
/* Save the context */
|
||||
timer->context.tier &= ~mask;
|
||||
timer->context.twer &= ~mask;
|
||||
omap_dm_timer_disable(timer);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
|
||||
|
||||
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
|
||||
{
|
||||
unsigned int l;
|
||||
@ -693,8 +708,7 @@ int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
|
||||
return -EINVAL;
|
||||
|
||||
__omap_dm_timer_write_status(timer, value);
|
||||
/* Save the context */
|
||||
timer->context.tisr = value;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
|
||||
@ -797,6 +811,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
|
||||
timer->capability |= OMAP_TIMER_SECURE;
|
||||
} else {
|
||||
timer->id = pdev->id;
|
||||
timer->errata = pdata->timer_errata;
|
||||
timer->capability = pdata->timer_capability;
|
||||
timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
|
||||
timer->get_context_loss_count = pdata->get_context_loss_count;
|
||||
|
||||
@ -32,7 +32,6 @@
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
@ -55,6 +54,10 @@
|
||||
#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
|
||||
#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
|
||||
|
||||
/* posted mode types */
|
||||
#define OMAP_TIMER_NONPOSTED 0x00
|
||||
#define OMAP_TIMER_POSTED 0x01
|
||||
|
||||
/* timer capabilities used in hwmod database */
|
||||
#define OMAP_TIMER_SECURE 0x80000000
|
||||
#define OMAP_TIMER_ALWON 0x40000000
|
||||
@ -62,6 +65,16 @@
|
||||
#define OMAP_TIMER_NEEDS_RESET 0x10000000
|
||||
#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
|
||||
|
||||
/*
|
||||
* timer errata flags
|
||||
*
|
||||
* Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
|
||||
* errata prevents us from using posted mode on these devices, unless the
|
||||
* timer counter register is never read. For more details please refer to
|
||||
* the OMAP3/4/5 errata documents.
|
||||
*/
|
||||
#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
|
||||
|
||||
struct omap_timer_capability_dev_attr {
|
||||
u32 timer_capability;
|
||||
};
|
||||
@ -70,8 +83,6 @@ struct omap_dm_timer;
|
||||
|
||||
struct timer_regs {
|
||||
u32 tidr;
|
||||
u32 tistat;
|
||||
u32 tisr;
|
||||
u32 tier;
|
||||
u32 twer;
|
||||
u32 tclr;
|
||||
@ -93,6 +104,7 @@ struct timer_regs {
|
||||
struct dmtimer_platform_data {
|
||||
/* set_timer_src - Only used for OMAP1 devices */
|
||||
int (*set_timer_src)(struct platform_device *pdev, int source);
|
||||
u32 timer_errata;
|
||||
u32 timer_capability;
|
||||
int (*get_context_loss_count)(struct device *);
|
||||
};
|
||||
@ -122,6 +134,7 @@ int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, i
|
||||
int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
|
||||
|
||||
int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
|
||||
int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask);
|
||||
|
||||
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
|
||||
int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
|
||||
@ -269,6 +282,7 @@ struct omap_dm_timer {
|
||||
int ctx_loss_count;
|
||||
int revision;
|
||||
u32 capability;
|
||||
u32 errata;
|
||||
struct platform_device *pdev;
|
||||
struct list_head node;
|
||||
};
|
||||
@ -307,7 +321,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
|
||||
OMAP_TIMER_V1_SYS_STAT_OFFSET;
|
||||
timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
|
||||
timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
|
||||
timer->irq_dis = NULL;
|
||||
timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
|
||||
timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
|
||||
timer->func_base = timer->io_base;
|
||||
} else {
|
||||
@ -340,28 +354,46 @@ static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
|
||||
l |= 1 << 2;
|
||||
|
||||
__raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
|
||||
|
||||
/* Match hardware reset default of posted mode */
|
||||
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
|
||||
OMAP_TIMER_CTRL_POSTED, 0);
|
||||
}
|
||||
|
||||
static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
|
||||
struct clk *parent)
|
||||
/*
|
||||
* __omap_dm_timer_enable_posted - enables write posted mode
|
||||
* @timer: pointer to timer instance handle
|
||||
*
|
||||
* Enables the write posted mode for the timer. When posted mode is enabled
|
||||
* writes to certain timer registers are immediately acknowledged by the
|
||||
* internal bus and hence prevents stalling the CPU waiting for the write to
|
||||
* complete. Enabling this feature can improve performance for writing to the
|
||||
* timer registers.
|
||||
*/
|
||||
static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
|
||||
{
|
||||
int ret;
|
||||
if (timer->posted)
|
||||
return;
|
||||
|
||||
clk_disable(timer_fck);
|
||||
ret = clk_set_parent(timer_fck, parent);
|
||||
clk_enable(timer_fck);
|
||||
if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
|
||||
return;
|
||||
|
||||
/*
|
||||
* When the functional clock disappears, too quick writes seem
|
||||
* to cause an abort. XXX Is this still necessary?
|
||||
*/
|
||||
__delay(300000);
|
||||
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
|
||||
OMAP_TIMER_CTRL_POSTED, 0);
|
||||
timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
|
||||
timer->posted = OMAP_TIMER_POSTED;
|
||||
}
|
||||
|
||||
return ret;
|
||||
/**
|
||||
* __omap_dm_timer_override_errata - override errata flags for a timer
|
||||
* @timer: pointer to timer handle
|
||||
* @errata: errata flags to be ignored
|
||||
*
|
||||
* For a given timer, override a timer errata by clearing the flags
|
||||
* specified by the errata argument. A specific erratum should only be
|
||||
* overridden for a timer if the timer is used in such a way the erratum
|
||||
* has no impact.
|
||||
*/
|
||||
static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
|
||||
u32 errata)
|
||||
{
|
||||
timer->errata &= ~errata;
|
||||
}
|
||||
|
||||
static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user