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drm/amdgpu/discovery: add module param for ip discovery enablement
to control enablement. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -161,6 +161,7 @@ extern int amdgpu_ras_enable;
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extern uint amdgpu_ras_mask;
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extern int amdgpu_async_gfx_ring;
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extern int amdgpu_mcbp;
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extern int amdgpu_discovery;
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#ifdef CONFIG_DRM_AMDGPU_SI
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extern int amdgpu_si_support;
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@ -2578,6 +2578,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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if (amdgpu_mcbp)
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DRM_INFO("MCBP is enabled\n");
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if (amdgpu_discovery) {
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r = amdgpu_discovery_init(adev);
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if (r) {
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dev_err(adev->dev, "amdgpu_discovery_init failed\n");
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return r;
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}
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}
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/* early init functions */
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r = amdgpu_device_ip_early_init(adev);
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if (r)
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@ -2838,6 +2846,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
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amdgpu_ucode_sysfs_fini(adev);
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amdgpu_pmu_fini(adev);
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amdgpu_debugfs_preempt_cleanup(adev);
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if (amdgpu_discovery)
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amdgpu_discovery_fini(adev);
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}
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@ -138,6 +138,7 @@ uint amdgpu_smu_memory_pool_size = 0;
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uint amdgpu_dc_feature_mask = 0;
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int amdgpu_async_gfx_ring = 1;
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int amdgpu_mcbp = 0;
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int amdgpu_discovery = 0;
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struct amdgpu_mgpu_info mgpu_info = {
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.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
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@ -579,6 +580,10 @@ MODULE_PARM_DESC(mcbp,
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"Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
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module_param_named(mcbp, amdgpu_mcbp, int, 0444);
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MODULE_PARM_DESC(discovery,
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"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
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module_param_named(discovery, amdgpu_discovery, int, 0444);
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#ifdef CONFIG_HSA_AMD
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/**
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* DOC: sched_policy (int)
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