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IB/ipath: Allow more flexible user register alignments
User registers have different alignments on different chips (4KB on older, 64KB on 7220). Allow mapping the user registers on kernels with page sizes up to 64K. Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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@ -169,7 +169,7 @@ static int ipath_get_base_info(struct file *fp,
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kinfo->spi_piocnt = dd->ipath_pbufsport;
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kinfo->spi_piocnt = dd->ipath_pbufsport;
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kinfo->spi_piobufbase = (u64) pd->port_piobufs;
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kinfo->spi_piobufbase = (u64) pd->port_piobufs;
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kinfo->__spi_uregbase = (u64) dd->ipath_uregbase +
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kinfo->__spi_uregbase = (u64) dd->ipath_uregbase +
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dd->ipath_palign * pd->port_port;
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dd->ipath_ureg_align * pd->port_port;
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} else if (master) {
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} else if (master) {
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kinfo->spi_piocnt = (dd->ipath_pbufsport / subport_cnt) +
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kinfo->spi_piocnt = (dd->ipath_pbufsport / subport_cnt) +
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(dd->ipath_pbufsport % subport_cnt);
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(dd->ipath_pbufsport % subport_cnt);
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@ -186,7 +186,7 @@ static int ipath_get_base_info(struct file *fp,
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}
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}
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if (shared) {
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if (shared) {
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kinfo->spi_port_uregbase = (u64) dd->ipath_uregbase +
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kinfo->spi_port_uregbase = (u64) dd->ipath_uregbase +
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dd->ipath_palign * pd->port_port;
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dd->ipath_ureg_align * pd->port_port;
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kinfo->spi_port_rcvegrbuf = kinfo->spi_rcv_egrbufs;
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kinfo->spi_port_rcvegrbuf = kinfo->spi_rcv_egrbufs;
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kinfo->spi_port_rcvhdr_base = kinfo->spi_rcvhdr_base;
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kinfo->spi_port_rcvhdr_base = kinfo->spi_rcvhdr_base;
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kinfo->spi_port_rcvhdr_tailaddr = kinfo->spi_rcvhdr_tailaddr;
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kinfo->spi_port_rcvhdr_tailaddr = kinfo->spi_rcvhdr_tailaddr;
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@ -1271,7 +1271,7 @@ static int ipath_mmap(struct file *fp, struct vm_area_struct *vma)
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goto bail;
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goto bail;
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}
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}
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ureg = dd->ipath_uregbase + dd->ipath_palign * pd->port_port;
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ureg = dd->ipath_uregbase + dd->ipath_ureg_align * pd->port_port;
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if (!pd->port_subport_cnt) {
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if (!pd->port_subport_cnt) {
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/* port is not shared */
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/* port is not shared */
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piocnt = dd->ipath_pbufsport;
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piocnt = dd->ipath_pbufsport;
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@ -739,6 +739,13 @@ static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
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dd->ipath_htspeed);
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dd->ipath_htspeed);
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ret = 0;
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ret = 0;
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/*
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* set here, not in ipath_init_*_funcs because we have to do
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* it after we can read chip registers.
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*/
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dd->ipath_ureg_align =
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ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
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bail:
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bail:
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return ret;
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return ret;
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}
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}
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@ -613,6 +613,14 @@ static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
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dd->ipath_f_put_tid = ipath_pe_put_tid_2;
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dd->ipath_f_put_tid = ipath_pe_put_tid_2;
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}
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}
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/*
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* set here, not in ipath_init_*_funcs because we have to do
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* it after we can read chip registers.
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*/
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dd->ipath_ureg_align =
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ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
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return ret;
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return ret;
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}
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}
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@ -395,6 +395,8 @@ struct ipath_devdata {
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void *ipath_dummy_hdrq; /* used after port close */
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void *ipath_dummy_hdrq; /* used after port close */
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dma_addr_t ipath_dummy_hdrq_phys;
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dma_addr_t ipath_dummy_hdrq_phys;
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unsigned long ipath_ureg_align; /* user register alignment */
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/*
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/*
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* Shadow copies of registers; size indicates read access size.
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* Shadow copies of registers; size indicates read access size.
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* Most of them are readonly, but some are write-only register,
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* Most of them are readonly, but some are write-only register,
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@ -865,7 +867,7 @@ static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
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return readl(regno + (u64 __iomem *)
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return readl(regno + (u64 __iomem *)
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(dd->ipath_uregbase +
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(dd->ipath_uregbase +
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(char __iomem *)dd->ipath_kregbase +
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(char __iomem *)dd->ipath_kregbase +
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dd->ipath_palign * port));
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dd->ipath_ureg_align * port));
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}
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}
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/**
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/**
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@ -882,7 +884,7 @@ static inline void ipath_write_ureg(const struct ipath_devdata *dd,
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{
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{
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u64 __iomem *ubase = (u64 __iomem *)
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u64 __iomem *ubase = (u64 __iomem *)
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(dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
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(dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
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dd->ipath_palign * port);
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dd->ipath_ureg_align * port);
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if (dd->ipath_kregbase)
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if (dd->ipath_kregbase)
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writeq(value, &ubase[regno]);
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writeq(value, &ubase[regno]);
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}
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}
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