mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 11:30:53 +07:00
mips: switch to ->regset_get()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
This commit is contained in:
Al Viro
parent
4d617aaae4
commit
a0faf966a4
@ -210,15 +210,13 @@ int ptrace_set_watch_regs(struct task_struct *child,
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static int gpr32_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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struct membuf to)
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{
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struct pt_regs *regs = task_pt_regs(target);
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u32 uregs[ELF_NGREG] = {};
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mips_dump_regs32(uregs, regs);
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return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
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sizeof(uregs));
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return membuf_write(&to, uregs, sizeof(uregs));
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}
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static int gpr32_set(struct task_struct *target,
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@ -277,15 +275,13 @@ static int gpr32_set(struct task_struct *target,
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static int gpr64_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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struct membuf to)
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{
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struct pt_regs *regs = task_pt_regs(target);
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u64 uregs[ELF_NGREG] = {};
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mips_dump_regs64(uregs, regs);
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return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
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sizeof(uregs));
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return membuf_write(&to, uregs, sizeof(uregs));
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}
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static int gpr64_set(struct task_struct *target,
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@ -408,13 +404,11 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
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* !CONFIG_CPU_HAS_MSA variant. FP context's general register slots
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* correspond 1:1 to buffer slots. Only general registers are copied.
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*/
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static int fpr_get_fpa(struct task_struct *target,
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unsigned int *pos, unsigned int *count,
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void **kbuf, void __user **ubuf)
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static void fpr_get_fpa(struct task_struct *target,
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struct membuf *to)
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{
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return user_regset_copyout(pos, count, kbuf, ubuf,
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&target->thread.fpu,
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0, NUM_FPU_REGS * sizeof(elf_fpreg_t));
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membuf_write(to, &target->thread.fpu,
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NUM_FPU_REGS * sizeof(elf_fpreg_t));
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}
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/*
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@ -423,25 +417,13 @@ static int fpr_get_fpa(struct task_struct *target,
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* general register slots are copied to buffer slots. Only general
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* registers are copied.
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*/
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static int fpr_get_msa(struct task_struct *target,
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unsigned int *pos, unsigned int *count,
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void **kbuf, void __user **ubuf)
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static void fpr_get_msa(struct task_struct *target, struct membuf *to)
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{
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unsigned int i;
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u64 fpr_val;
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int err;
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BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));
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for (i = 0; i < NUM_FPU_REGS; i++) {
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fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);
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err = user_regset_copyout(pos, count, kbuf, ubuf,
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&fpr_val, i * sizeof(elf_fpreg_t),
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(i + 1) * sizeof(elf_fpreg_t));
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if (err)
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return err;
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}
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return 0;
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BUILD_BUG_ON(sizeof(u64) != sizeof(elf_fpreg_t));
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for (i = 0; i < NUM_FPU_REGS; i++)
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membuf_store(to, get_fpr64(&target->thread.fpu.fpr[i], 0));
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}
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/*
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@ -451,31 +433,16 @@ static int fpr_get_msa(struct task_struct *target,
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*/
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static int fpr_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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struct membuf to)
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{
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const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
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const int fir_pos = fcr31_pos + sizeof(u32);
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int err;
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if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
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err = fpr_get_fpa(target, &pos, &count, &kbuf, &ubuf);
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fpr_get_fpa(target, &to);
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else
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err = fpr_get_msa(target, &pos, &count, &kbuf, &ubuf);
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if (err)
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return err;
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fpr_get_msa(target, &to);
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err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&target->thread.fpu.fcr31,
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fcr31_pos, fcr31_pos + sizeof(u32));
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if (err)
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return err;
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err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&boot_cpu_data.fpu_id,
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fir_pos, fir_pos + sizeof(u32));
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return err;
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membuf_write(&to, &target->thread.fpu.fcr31, sizeof(u32));
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membuf_write(&to, &boot_cpu_data.fpu_id, sizeof(u32));
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return 0;
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}
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/*
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@ -576,14 +543,9 @@ static int fpr_set(struct task_struct *target,
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/* Copy the FP mode setting to the supplied NT_MIPS_FP_MODE buffer. */
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static int fp_mode_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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struct membuf to)
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{
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int fp_mode;
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fp_mode = mips_get_process_fp_mode(target);
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return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &fp_mode, 0,
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sizeof(fp_mode));
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return membuf_store(&to, (int)mips_get_process_fp_mode(target));
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}
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/*
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@ -630,13 +592,12 @@ struct msa_control_regs {
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unsigned int msacsr;
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};
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static int copy_pad_fprs(struct task_struct *target,
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static void copy_pad_fprs(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int *ppos, unsigned int *pcount,
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void **pkbuf, void __user **pubuf,
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struct membuf *to,
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unsigned int live_sz)
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{
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int i, j, start, start_pad, err;
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int i, j;
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unsigned long long fill = ~0ull;
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unsigned int cp_sz, pad_sz;
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@ -644,28 +605,16 @@ static int copy_pad_fprs(struct task_struct *target,
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pad_sz = regset->size - cp_sz;
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WARN_ON(pad_sz % sizeof(fill));
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i = start = err = 0;
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for (; i < NUM_FPU_REGS; i++, start += regset->size) {
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err |= user_regset_copyout(ppos, pcount, pkbuf, pubuf,
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&target->thread.fpu.fpr[i],
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start, start + cp_sz);
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start_pad = start + cp_sz;
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for (j = 0; j < (pad_sz / sizeof(fill)); j++) {
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err |= user_regset_copyout(ppos, pcount, pkbuf, pubuf,
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&fill, start_pad,
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start_pad + sizeof(fill));
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start_pad += sizeof(fill);
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for (i = 0; i < NUM_FPU_REGS; i++) {
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membuf_write(to, &target->thread.fpu.fpr[i], cp_sz);
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for (j = 0; j < (pad_sz / sizeof(fill)); j++)
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membuf_store(to, fill);
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}
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}
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return err;
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}
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static int msa_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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struct membuf to)
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{
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const unsigned int wr_size = NUM_FPU_REGS * regset->size;
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const struct msa_control_regs ctrl_regs = {
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@ -674,32 +623,23 @@ static int msa_get(struct task_struct *target,
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.msair = boot_cpu_data.msa_id,
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.msacsr = target->thread.fpu.msacsr,
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};
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int err;
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if (!tsk_used_math(target)) {
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/* The task hasn't used FP or MSA, fill with 0xff */
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err = copy_pad_fprs(target, regset, &pos, &count,
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&kbuf, &ubuf, 0);
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copy_pad_fprs(target, regset, &to, 0);
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} else if (!test_tsk_thread_flag(target, TIF_MSA_CTX_LIVE)) {
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/* Copy scalar FP context, fill the rest with 0xff */
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err = copy_pad_fprs(target, regset, &pos, &count,
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&kbuf, &ubuf, 8);
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copy_pad_fprs(target, regset, &to, 8);
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} else if (sizeof(target->thread.fpu.fpr[0]) == regset->size) {
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/* Trivially copy the vector registers */
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err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&target->thread.fpu.fpr,
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0, wr_size);
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membuf_write(&to, &target->thread.fpu.fpr, wr_size);
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} else {
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/* Copy as much context as possible, fill the rest with 0xff */
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err = copy_pad_fprs(target, regset, &pos, &count,
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&kbuf, &ubuf,
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copy_pad_fprs(target, regset, &to,
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sizeof(target->thread.fpu.fpr[0]));
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}
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err |= user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&ctrl_regs, wr_size,
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wr_size + sizeof(ctrl_regs));
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return err;
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return membuf_write(&to, &ctrl_regs, sizeof(ctrl_regs));
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}
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static int msa_set(struct task_struct *target,
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@ -752,34 +692,20 @@ static int msa_set(struct task_struct *target,
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*/
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static int dsp32_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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struct membuf to)
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{
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unsigned int start, num_regs, i;
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u32 dspregs[NUM_DSP_REGS + 1];
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unsigned int i;
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BUG_ON(count % sizeof(u32));
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BUG_ON(to.left % sizeof(u32));
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if (!cpu_has_dsp)
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return -EIO;
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start = pos / sizeof(u32);
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num_regs = count / sizeof(u32);
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if (start + num_regs > NUM_DSP_REGS + 1)
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return -EIO;
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for (i = start; i < num_regs; i++)
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switch (i) {
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case 0 ... NUM_DSP_REGS - 1:
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for (i = 0; i < NUM_DSP_REGS; i++)
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dspregs[i] = target->thread.dsp.dspr[i];
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break;
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case NUM_DSP_REGS:
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dspregs[i] = target->thread.dsp.dspcontrol;
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break;
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}
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return user_regset_copyout(&pos, &count, &kbuf, &ubuf, dspregs, 0,
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sizeof(dspregs));
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dspregs[NUM_DSP_REGS] = target->thread.dsp.dspcontrol;
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return membuf_write(&to, dspregs, sizeof(dspregs));
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}
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/*
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@ -832,34 +758,20 @@ static int dsp32_set(struct task_struct *target,
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*/
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static int dsp64_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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struct membuf to)
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{
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unsigned int start, num_regs, i;
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u64 dspregs[NUM_DSP_REGS + 1];
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unsigned int i;
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BUG_ON(count % sizeof(u64));
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BUG_ON(to.left % sizeof(u64));
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if (!cpu_has_dsp)
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return -EIO;
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start = pos / sizeof(u64);
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num_regs = count / sizeof(u64);
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if (start + num_regs > NUM_DSP_REGS + 1)
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return -EIO;
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for (i = start; i < num_regs; i++)
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switch (i) {
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case 0 ... NUM_DSP_REGS - 1:
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for (i = 0; i < NUM_DSP_REGS; i++)
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dspregs[i] = target->thread.dsp.dspr[i];
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break;
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case NUM_DSP_REGS:
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dspregs[i] = target->thread.dsp.dspcontrol;
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break;
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}
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return user_regset_copyout(&pos, &count, &kbuf, &ubuf, dspregs, 0,
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sizeof(dspregs));
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dspregs[NUM_DSP_REGS] = target->thread.dsp.dspcontrol;
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return membuf_write(&to, dspregs, sizeof(dspregs));
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}
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/*
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@ -1018,7 +930,7 @@ static const struct user_regset mips_regsets[] = {
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.n = ELF_NGREG,
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.size = sizeof(unsigned int),
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.align = sizeof(unsigned int),
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.get = gpr32_get,
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.regset_get = gpr32_get,
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.set = gpr32_set,
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},
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[REGSET_DSP] = {
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@ -1026,7 +938,7 @@ static const struct user_regset mips_regsets[] = {
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.n = NUM_DSP_REGS + 1,
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.size = sizeof(u32),
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.align = sizeof(u32),
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.get = dsp32_get,
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.regset_get = dsp32_get,
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.set = dsp32_set,
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.active = dsp_active,
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},
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@ -1036,7 +948,7 @@ static const struct user_regset mips_regsets[] = {
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.n = ELF_NFPREG,
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.size = sizeof(elf_fpreg_t),
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.align = sizeof(elf_fpreg_t),
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.get = fpr_get,
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.regset_get = fpr_get,
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.set = fpr_set,
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},
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[REGSET_FP_MODE] = {
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@ -1044,7 +956,7 @@ static const struct user_regset mips_regsets[] = {
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.n = 1,
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.size = sizeof(int),
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.align = sizeof(int),
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.get = fp_mode_get,
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.regset_get = fp_mode_get,
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.set = fp_mode_set,
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},
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#endif
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@ -1054,7 +966,7 @@ static const struct user_regset mips_regsets[] = {
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.n = NUM_FPU_REGS + 1,
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.size = 16,
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.align = 16,
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.get = msa_get,
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.regset_get = msa_get,
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.set = msa_set,
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},
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#endif
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@ -1078,7 +990,7 @@ static const struct user_regset mips64_regsets[] = {
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.n = ELF_NGREG,
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.size = sizeof(unsigned long),
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.align = sizeof(unsigned long),
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.get = gpr64_get,
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.regset_get = gpr64_get,
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.set = gpr64_set,
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},
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[REGSET_DSP] = {
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@ -1086,7 +998,7 @@ static const struct user_regset mips64_regsets[] = {
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.n = NUM_DSP_REGS + 1,
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.size = sizeof(u64),
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.align = sizeof(u64),
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.get = dsp64_get,
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.regset_get = dsp64_get,
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.set = dsp64_set,
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.active = dsp_active,
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},
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@ -1096,7 +1008,7 @@ static const struct user_regset mips64_regsets[] = {
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.n = 1,
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.size = sizeof(int),
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.align = sizeof(int),
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.get = fp_mode_get,
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.regset_get = fp_mode_get,
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.set = fp_mode_set,
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},
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[REGSET_FPR] = {
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@ -1104,7 +1016,7 @@ static const struct user_regset mips64_regsets[] = {
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.n = ELF_NFPREG,
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.size = sizeof(elf_fpreg_t),
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.align = sizeof(elf_fpreg_t),
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.get = fpr_get,
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.regset_get = fpr_get,
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.set = fpr_set,
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},
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#endif
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@ -1114,7 +1026,7 @@ static const struct user_regset mips64_regsets[] = {
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.n = NUM_FPU_REGS + 1,
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.size = 16,
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.align = 16,
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.get = msa_get,
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.regset_get = msa_get,
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.set = msa_set,
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},
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#endif
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