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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 17:46:47 +07:00
sfc: process RX event inner checksum flags
Add support for RX checksum offload of encapsulated packets. This essentially just means paying attention to the inner checksum flags in the RX event, and if *either* checksum flag indicates a fail then don't tell the kernel that checksum offload was successful. Also, count these checksum errors and export the counts to ethtool -S. Test the most common "good" case of RX events with a single bitmask instead of a series of ifs. Move the more specific error checking in to a separate function for clarity, and don't use unlikely() there since we know at least one of the bits is bad. Signed-off-by: Edward Cree <ecree@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -433,6 +433,9 @@ typedef union efx_oword {
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(oword).u64[1] = (from).u64[1] & (mask).u64[1]; \
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} while (0)
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#define EFX_AND_QWORD(qword, from, mask) \
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(qword).u64[0] = (from).u64[0] & (mask).u64[0]
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#define EFX_OR_OWORD(oword, from, mask) \
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do { \
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(oword).u64[0] = (from).u64[0] | (mask).u64[0]; \
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@ -3154,13 +3154,103 @@ static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
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++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
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}
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static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
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unsigned int n_packets,
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unsigned int rx_encap_hdr,
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unsigned int rx_l3_class,
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unsigned int rx_l4_class,
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const efx_qword_t *event)
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{
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struct efx_nic *efx = channel->efx;
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if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
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if (!efx->loopback_selftest)
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channel->n_rx_eth_crc_err += n_packets;
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return EFX_RX_PKT_DISCARD;
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}
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if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
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if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
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rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
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rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
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rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
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rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
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netdev_WARN(efx->net_dev,
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"invalid class for RX_IPCKSUM_ERR: event="
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EFX_QWORD_FMT "\n",
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EFX_QWORD_VAL(*event));
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if (!efx->loopback_selftest)
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*(rx_encap_hdr ?
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&channel->n_rx_outer_ip_hdr_chksum_err :
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&channel->n_rx_ip_hdr_chksum_err) += n_packets;
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return 0;
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}
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if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
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if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
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((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
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rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
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(rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
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rx_l4_class != ESE_DZ_L4_CLASS_UDP))))
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netdev_WARN(efx->net_dev,
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"invalid class for RX_TCPUDP_CKSUM_ERR: event="
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EFX_QWORD_FMT "\n",
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EFX_QWORD_VAL(*event));
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if (!efx->loopback_selftest)
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*(rx_encap_hdr ?
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&channel->n_rx_outer_tcp_udp_chksum_err :
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&channel->n_rx_tcp_udp_chksum_err) += n_packets;
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return 0;
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}
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if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
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if (unlikely(!rx_encap_hdr))
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netdev_WARN(efx->net_dev,
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"invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
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EFX_QWORD_FMT "\n",
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EFX_QWORD_VAL(*event));
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else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
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rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
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rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
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rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
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netdev_WARN(efx->net_dev,
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"invalid class for RX_IP_INNER_CHKSUM_ERR: event="
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EFX_QWORD_FMT "\n",
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EFX_QWORD_VAL(*event));
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if (!efx->loopback_selftest)
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channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
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return 0;
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}
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if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
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if (unlikely(!rx_encap_hdr))
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netdev_WARN(efx->net_dev,
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"invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
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EFX_QWORD_FMT "\n",
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EFX_QWORD_VAL(*event));
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else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
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rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
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(rx_l4_class != ESE_DZ_L4_CLASS_TCP &&
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rx_l4_class != ESE_DZ_L4_CLASS_UDP)))
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netdev_WARN(efx->net_dev,
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"invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
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EFX_QWORD_FMT "\n",
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EFX_QWORD_VAL(*event));
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if (!efx->loopback_selftest)
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channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
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return 0;
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}
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WARN_ON(1); /* No error bits were recognised */
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return 0;
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}
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static int efx_ef10_handle_rx_event(struct efx_channel *channel,
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const efx_qword_t *event)
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{
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unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
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unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
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unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
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unsigned int n_descs, n_packets, i;
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struct efx_nic *efx = channel->efx;
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struct efx_ef10_nic_data *nic_data = efx->nic_data;
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struct efx_rx_queue *rx_queue;
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efx_qword_t errors;
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bool rx_cont;
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u16 flags = 0;
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@ -3171,8 +3261,14 @@ static int efx_ef10_handle_rx_event(struct efx_channel *channel,
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rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
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next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
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rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
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rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
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rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
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rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
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rx_encap_hdr =
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nic_data->datapath_caps &
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(1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
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EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
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ESE_EZ_ENCAP_HDR_NONE;
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if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
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netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
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@ -3232,17 +3328,20 @@ static int efx_ef10_handle_rx_event(struct efx_channel *channel,
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n_packets = 1;
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}
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if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
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flags |= EFX_RX_PKT_DISCARD;
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if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
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channel->n_rx_ip_hdr_chksum_err += n_packets;
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} else if (unlikely(EFX_QWORD_FIELD(*event,
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ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
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channel->n_rx_tcp_udp_chksum_err += n_packets;
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} else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
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rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
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flags |= EFX_RX_PKT_CSUMMED;
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EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
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ESF_DZ_RX_IPCKSUM_ERR, 1,
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ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
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ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
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ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
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EFX_AND_QWORD(errors, *event, errors);
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if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
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flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
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rx_l3_class, rx_l4_class,
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rx_encap_hdr, event);
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} else {
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if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
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rx_l4_class == ESE_DZ_L4_CLASS_UDP)
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flags |= EFX_RX_PKT_CSUMMED;
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}
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if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
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@ -77,6 +77,11 @@ static const struct efx_sw_stat_desc efx_sw_stat_desc[] = {
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_tobe_disc),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_ip_hdr_chksum_err),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_tcp_udp_chksum_err),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_inner_ip_hdr_chksum_err),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_inner_tcp_udp_chksum_err),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_outer_ip_hdr_chksum_err),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_outer_tcp_udp_chksum_err),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_eth_crc_err),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_mcast_mismatch),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_frm_trunc),
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EFX_ETHTOOL_UINT_CHANNEL_STAT(rx_merge_events),
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@ -469,13 +469,18 @@ struct efx_channel {
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u32 *rps_flow_id;
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#endif
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unsigned n_rx_tobe_disc;
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unsigned n_rx_ip_hdr_chksum_err;
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unsigned n_rx_tcp_udp_chksum_err;
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unsigned n_rx_mcast_mismatch;
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unsigned n_rx_frm_trunc;
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unsigned n_rx_overlength;
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unsigned n_skbuff_leaks;
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unsigned int n_rx_tobe_disc;
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unsigned int n_rx_ip_hdr_chksum_err;
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unsigned int n_rx_tcp_udp_chksum_err;
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unsigned int n_rx_outer_ip_hdr_chksum_err;
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unsigned int n_rx_outer_tcp_udp_chksum_err;
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unsigned int n_rx_inner_ip_hdr_chksum_err;
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unsigned int n_rx_inner_tcp_udp_chksum_err;
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unsigned int n_rx_eth_crc_err;
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unsigned int n_rx_mcast_mismatch;
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unsigned int n_rx_frm_trunc;
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unsigned int n_rx_overlength;
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unsigned int n_skbuff_leaks;
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unsigned int n_rx_nodesc_trunc;
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unsigned int n_rx_merge_events;
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unsigned int n_rx_merge_packets;
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