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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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tty: serial: fsl_lpuart: fix DMA mapping
Use the correct device to request the DMA mapping. Otherwise the IOMMU doesn't get the mapping and it will generate a page fault. The error messages look like: [ 19.012140] arm-smmu 5000000.iommu: Unhandled context fault: fsr=0x402, iova=0xbbfff800, fsynr=0x3e0021, cbfrsynra=0x828, cb=9 [ 19.023593] arm-smmu 5000000.iommu: Unhandled context fault: fsr=0x402, iova=0xbbfff800, fsynr=0x3e0021, cbfrsynra=0x828, cb=9 This was tested on a custom board with a LS1028A SoC. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20200306214433.23215-3-michael@walle.cc Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -409,6 +409,7 @@ static void lpuart_dma_tx(struct lpuart_port *sport)
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struct circ_buf *xmit = &sport->port.state->xmit;
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struct scatterlist *sgl = sport->tx_sgl;
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struct device *dev = sport->port.dev;
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struct dma_chan *chan = sport->dma_tx_chan;
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int ret;
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if (sport->dma_tx_in_progress)
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@ -427,17 +428,19 @@ static void lpuart_dma_tx(struct lpuart_port *sport)
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sg_set_buf(sgl + 1, xmit->buf, xmit->head);
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}
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ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
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ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
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DMA_TO_DEVICE);
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if (!ret) {
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dev_err(dev, "DMA mapping error for TX.\n");
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return;
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}
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sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
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sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
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ret, DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT);
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if (!sport->dma_tx_desc) {
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dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
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dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
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DMA_TO_DEVICE);
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dev_err(dev, "Cannot prepare TX slave DMA!\n");
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return;
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}
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@ -446,7 +449,7 @@ static void lpuart_dma_tx(struct lpuart_port *sport)
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sport->dma_tx_desc->callback_param = sport;
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sport->dma_tx_in_progress = true;
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sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
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dma_async_issue_pending(sport->dma_tx_chan);
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dma_async_issue_pending(chan);
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}
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static bool lpuart_stopped_or_empty(struct uart_port *port)
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@ -459,11 +462,13 @@ static void lpuart_dma_tx_complete(void *arg)
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struct lpuart_port *sport = arg;
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struct scatterlist *sgl = &sport->tx_sgl[0];
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struct circ_buf *xmit = &sport->port.state->xmit;
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struct dma_chan *chan = sport->dma_tx_chan;
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unsigned long flags;
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spin_lock_irqsave(&sport->port.lock, flags);
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dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
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dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
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DMA_TO_DEVICE);
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xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
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@ -529,15 +534,16 @@ static bool lpuart_is_32(struct lpuart_port *sport)
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static void lpuart_flush_buffer(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
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struct dma_chan *chan = sport->dma_tx_chan;
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u32 val;
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if (sport->lpuart_dma_tx_use) {
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if (sport->dma_tx_in_progress) {
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dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
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dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
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sport->dma_tx_nents, DMA_TO_DEVICE);
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sport->dma_tx_in_progress = false;
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}
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dmaengine_terminate_all(sport->dma_tx_chan);
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dmaengine_terminate_all(chan);
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}
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if (lpuart_is_32(sport)) {
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@ -993,6 +999,7 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
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struct tty_port *port = &sport->port.state->port;
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struct dma_tx_state state;
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enum dma_status dmastat;
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struct dma_chan *chan = sport->dma_rx_chan;
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struct circ_buf *ring = &sport->rx_ring;
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unsigned long flags;
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int count = 0;
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@ -1053,10 +1060,7 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
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spin_lock_irqsave(&sport->port.lock, flags);
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dmastat = dmaengine_tx_status(sport->dma_rx_chan,
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sport->dma_rx_cookie,
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&state);
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dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
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if (dmastat == DMA_ERROR) {
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dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
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spin_unlock_irqrestore(&sport->port.lock, flags);
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@ -1064,7 +1068,8 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
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}
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/* CPU claims ownership of RX DMA buffer */
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dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
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dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
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DMA_FROM_DEVICE);
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/*
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* ring->head points to the end of data already written by the DMA.
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@ -1106,7 +1111,7 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
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sport->port.icount.rx += count;
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}
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dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
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dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
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DMA_FROM_DEVICE);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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@ -1138,6 +1143,7 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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struct tty_port *port = &sport->port.state->port;
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struct tty_struct *tty = port->tty;
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struct ktermios *termios = &tty->termios;
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struct dma_chan *chan = sport->dma_rx_chan;
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baud = tty_get_baud_rate(tty);
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@ -1159,7 +1165,8 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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return -ENOMEM;
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sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
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nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
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nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
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DMA_FROM_DEVICE);
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if (!nent) {
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dev_err(sport->port.dev, "DMA Rx mapping error\n");
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@ -1170,7 +1177,7 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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dma_rx_sconfig.src_maxburst = 1;
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dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
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ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
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ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
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if (ret < 0) {
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dev_err(sport->port.dev,
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@ -1178,7 +1185,7 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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return ret;
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}
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sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
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sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
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sg_dma_address(&sport->rx_sgl),
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sport->rx_sgl.length,
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sport->rx_sgl.length / 2,
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@ -1192,7 +1199,7 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
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sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
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sport->dma_rx_desc->callback_param = sport;
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sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
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dma_async_issue_pending(sport->dma_rx_chan);
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dma_async_issue_pending(chan);
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if (lpuart_is_32(sport)) {
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unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
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@ -1210,11 +1217,12 @@ static void lpuart_dma_rx_free(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port,
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struct lpuart_port, port);
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struct dma_chan *chan = sport->dma_rx_chan;
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if (sport->dma_rx_chan)
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dmaengine_terminate_all(sport->dma_rx_chan);
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if (chan)
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dmaengine_terminate_all(chan);
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dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
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dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
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kfree(sport->rx_ring.buf);
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sport->rx_ring.tail = 0;
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sport->rx_ring.head = 0;
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