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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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clk: stm32f469: Add QSPI clock
This patch adds the QSPI clock for stm32f469 discovery board. The gate mapping is a little bit different from stm32f429 soc. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Gabriel Fernandez
Stephen Boyd
parent
4261a881cf
commit
a064a07f72
@ -7,7 +7,9 @@ Please refer to clock-bindings.txt for common clock controller binding usage.
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Please also refer to reset.txt for common reset controller binding usage.
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Required properties:
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- compatible: Should be "st,stm32f42xx-rcc"
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- compatible: Should be:
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"st,stm32f42xx-rcc"
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"st,stm32f469-rcc"
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- reg: should be register base and length as documented in the
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datasheet
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- #reset-cells: 1, see below
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@ -46,7 +46,7 @@ struct stm32f4_gate_data {
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unsigned long flags;
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};
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static const struct stm32f4_gate_data stm32f4_gates[] __initconst = {
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static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
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{ STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
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@ -126,22 +126,108 @@ static const struct stm32f4_gate_data stm32f4_gates[] __initconst = {
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{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
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};
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static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
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{ STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
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{ STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
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{ STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
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{ STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
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{ STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
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{ STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
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{ STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
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CLK_IGNORE_UNUSED },
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{ STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
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CLK_IGNORE_UNUSED },
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{ STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
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{ STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
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{ STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
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};
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enum { SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC, END_PRIMARY_CLK };
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/*
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* MAX_CLKS is the maximum value in the enumeration below plus the combined
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* hweight of stm32f42xx_gate_map (plus one).
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*/
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#define MAX_CLKS (71 + END_PRIMARY_CLK + 1)
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/*
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* This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
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* have gate bits associated with them. Its combined hweight is 71.
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*/
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static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ffull,
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0x0000000000000001ull,
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0x04777f33f6fec9ffull };
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#define MAX_GATE_MAP 3
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static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
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0x0000000000000001ull,
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0x04777f33f6fec9ffull };
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static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
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0x0000000000000003ull,
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0x0c777f33f6fec9ffull };
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static const u64 *stm32f4_gate_map;
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static struct clk_hw **clks;
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static struct clk_hw *clks[MAX_CLKS];
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static DEFINE_SPINLOCK(stm32f4_clk_lock);
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static void __iomem *base;
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@ -263,7 +349,7 @@ static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk)
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*/
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static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
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{
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u64 table[ARRAY_SIZE(stm32f42xx_gate_map)];
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u64 table[MAX_GATE_MAP];
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if (primary == 1) {
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if (WARN_ON(secondary >= END_PRIMARY_CLK))
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@ -271,7 +357,7 @@ static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
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return secondary;
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}
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memcpy(table, stm32f42xx_gate_map, sizeof(table));
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memcpy(table, stm32f4_gate_map, sizeof(table));
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/* only bits set in table can be used as indices */
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if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
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@ -525,10 +611,42 @@ static const char *rtc_parents[4] = {
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"no-clock", "lse", "lsi", "hse-rtc"
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};
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struct stm32f4_clk_data {
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const struct stm32f4_gate_data *gates_data;
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const u64 *gates_map;
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int gates_num;
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};
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static const struct stm32f4_clk_data stm32f429_clk_data = {
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.gates_data = stm32f429_gates,
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.gates_map = stm32f42xx_gate_map,
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.gates_num = ARRAY_SIZE(stm32f429_gates),
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};
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static const struct stm32f4_clk_data stm32f469_clk_data = {
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.gates_data = stm32f469_gates,
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.gates_map = stm32f46xx_gate_map,
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.gates_num = ARRAY_SIZE(stm32f469_gates),
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};
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static const struct of_device_id stm32f4_of_match[] = {
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{
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.compatible = "st,stm32f42xx-rcc",
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.data = &stm32f429_clk_data
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},
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{
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.compatible = "st,stm32f469-rcc",
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.data = &stm32f469_clk_data
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},
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{}
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};
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static void __init stm32f4_rcc_init(struct device_node *np)
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{
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const char *hse_clk;
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int n;
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const struct of_device_id *match;
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const struct stm32f4_clk_data *data;
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base = of_iomap(np, 0);
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if (!base) {
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@ -542,6 +660,19 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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pr_warn("%s: Unable to get syscfg\n", __func__);
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}
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match = of_match_node(stm32f4_of_match, np);
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if (WARN_ON(!match))
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return;
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data = match->data;
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clks = kmalloc_array(data->gates_num + END_PRIMARY_CLK,
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sizeof(*clks), GFP_KERNEL);
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if (!clks)
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goto fail;
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stm32f4_gate_map = data->gates_map;
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hse_clk = of_clk_get_parent_name(np, 0);
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clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
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@ -574,11 +705,15 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
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0, 1, 1);
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for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) {
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const struct stm32f4_gate_data *gd = &stm32f4_gates[n];
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unsigned int secondary =
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8 * (gd->offset - STM32F4_RCC_AHB1ENR) + gd->bit_idx;
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int idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
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for (n = 0; n < data->gates_num; n++) {
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const struct stm32f4_gate_data *gd;
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unsigned int secondary;
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int idx;
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gd = &data->gates_data[n];
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secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
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gd->bit_idx;
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idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
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if (idx < 0)
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goto fail;
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@ -630,6 +765,8 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
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return;
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fail:
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kfree(clks);
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iounmap(base);
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}
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CLK_OF_DECLARE(stm32f4_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
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CLK_OF_DECLARE(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
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CLK_OF_DECLARE(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
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