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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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[media] drxd: convert set_fontend to use DVBv5 parameters
Instead of using dvb_frontend_parameters struct, that were designed for a subset of the supported standards, use the DVBv5 cache information. Also, fill the supported delivery systems at dvb_frontend_ops struct. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -48,8 +48,6 @@ struct drxd_config {
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u8 disable_i2c_gate_ctrl;
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u32 IF;
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int (*pll_set) (void *priv, void *priv_params,
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u8 pll_addr, u8 demoda_addr, s32 *off);
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s16(*osc_deviation) (void *priv, s16 dev, int flag);
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};
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@ -120,7 +120,7 @@ enum EIFFilter {
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struct drxd_state {
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struct dvb_frontend frontend;
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struct dvb_frontend_ops ops;
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struct dvb_frontend_parameters param;
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struct dtv_frontend_properties props;
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const struct firmware *fw;
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struct device *dev;
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@ -1621,14 +1621,14 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
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break;
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}
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switch (state->param.u.ofdm.bandwidth) {
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case BANDWIDTH_8_MHZ:
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switch (state->props.bandwidth_hz) {
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case 8000000:
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bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
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break;
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case BANDWIDTH_7_MHZ:
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case 7000000:
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bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
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break;
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case BANDWIDTH_6_MHZ:
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case 6000000:
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bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
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break;
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default:
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@ -1803,7 +1803,7 @@ static int StartDiversity(struct drxd_state *state)
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status = WriteTable(state, state->m_StartDiversityEnd);
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if (status < 0)
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break;
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if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
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if (state->props.bandwidth_hz == 8000000) {
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status = WriteTable(state, state->m_DiversityDelay8MHZ);
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if (status < 0)
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break;
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@ -1905,7 +1905,7 @@ static int SetCfgNoiseCalibration(struct drxd_state *state,
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static int DRX_Start(struct drxd_state *state, s32 off)
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{
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struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
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struct dtv_frontend_properties *p = &state->props;
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int status;
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u16 transmissionParams = 0;
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@ -1970,7 +1970,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
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if (status < 0)
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break;
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mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
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mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
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switch (p->transmission_mode) {
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default: /* Not set, detect it automatically */
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@ -2020,7 +2020,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
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break;
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}
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switch (p->hierarchy_information) {
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switch (p->hierarchy) {
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case HIERARCHY_1:
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transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
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if (state->type_A) {
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@ -2146,7 +2146,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
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if (status < 0)
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break;
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switch (p->constellation) {
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switch (p->modulation) {
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default:
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operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
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/* fall through , try first guess
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@ -2330,9 +2330,11 @@ static int DRX_Start(struct drxd_state *state, s32 off)
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by SC for fix for some 8K,1/8 guard but is restored by
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InitEC and ResetEC
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functions */
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switch (p->bandwidth) {
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case BANDWIDTH_AUTO:
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case BANDWIDTH_8_MHZ:
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switch (p->bandwidth_hz) {
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case 0:
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p->bandwidth_hz = 8000000;
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/* fall through */
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case 8000000:
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/* (64/7)*(8/8)*1000000 */
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bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
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@ -2340,14 +2342,14 @@ static int DRX_Start(struct drxd_state *state, s32 off)
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status = Write16(state,
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FE_AG_REG_IND_DEL__A, 50, 0x0000);
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break;
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case BANDWIDTH_7_MHZ:
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case 7000000:
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/* (64/7)*(7/8)*1000000 */
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bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
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bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
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status = Write16(state,
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FE_AG_REG_IND_DEL__A, 59, 0x0000);
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break;
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case BANDWIDTH_6_MHZ:
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case 6000000:
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/* (64/7)*(6/8)*1000000 */
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bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
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bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
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@ -2886,24 +2888,18 @@ static int drxd_sleep(struct dvb_frontend *fe)
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return 0;
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}
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static int drxd_get_frontend(struct dvb_frontend *fe,
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struct dvb_frontend_parameters *param)
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{
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return 0;
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}
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static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
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{
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return drxd_config_i2c(fe, enable);
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}
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static int drxd_set_frontend(struct dvb_frontend *fe,
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struct dvb_frontend_parameters *param)
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static int drxd_set_frontend(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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struct drxd_state *state = fe->demodulator_priv;
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s32 off = 0;
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state->param = *param;
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state->props = *p;
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DRX_Stop(state);
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if (fe->ops.tuner_ops.set_params) {
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@ -2912,15 +2908,6 @@ static int drxd_set_frontend(struct dvb_frontend *fe,
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fe->ops.i2c_gate_ctrl(fe, 0);
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}
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/* FIXME: move PLL drivers */
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if (state->config.pll_set &&
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state->config.pll_set(state->priv, param,
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state->config.pll_address,
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state->config.demoda_address, &off) < 0) {
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printk(KERN_ERR "Error in pll_set\n");
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return -1;
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}
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msleep(200);
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return DRX_Start(state, off);
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@ -2934,7 +2921,7 @@ static void drxd_release(struct dvb_frontend *fe)
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}
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static struct dvb_frontend_ops drxd_ops = {
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.delsys = { SYS_DVBT},
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.info = {
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.name = "Micronas DRXD DVB-T",
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.type = FE_OFDM,
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@ -2956,8 +2943,7 @@ static struct dvb_frontend_ops drxd_ops = {
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.sleep = drxd_sleep,
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.i2c_gate_ctrl = drxd_i2c_gate_ctrl,
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.set_frontend_legacy = drxd_set_frontend,
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.get_frontend_legacy = drxd_get_frontend,
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.set_frontend = drxd_set_frontend,
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.get_tune_settings = drxd_get_tune_settings,
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.read_status = drxd_read_status,
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