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Blackfin pata-bf54x driver: fix compiling bug - no ata_port struct in struct ata_device any more
Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -299,7 +299,7 @@ static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev)
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*/
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n6 = num_clocks_min(t6min, fsclk);
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if (mode >= 0 && mode <= 4 && n6 >= 1) {
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dev_dbg(adev->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
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dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
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/* calculate the timing values for register transfers. */
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while (mode > 0 && pio_fsclk[mode] > fsclk)
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mode--;
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@ -376,7 +376,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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mode = adev->dma_mode - XFER_UDMA_0;
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if (mode >= 0 && mode <= 5) {
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dev_dbg(adev->ap->dev, "set udmamode: mode=%d\n", mode);
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dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode);
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/* the most restrictive timing value is t6 and tc,
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* the DIOW - data hold. If one SCLK pulse is longer
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* than this minimum value then register
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@ -433,7 +433,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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mode = adev->dma_mode - XFER_MW_DMA_0;
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if (mode >= 0 && mode <= 2) {
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dev_dbg(adev->ap->dev, "set mdmamode: mode=%d\n", mode);
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dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode);
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/* the most restrictive timing value is tf, the DMACK to
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* read data released. If one SCLK pulse is longer than
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* this maximum value then the MDMA mode
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