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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-22 12:53:29 +07:00
drm/i915/fbc: Move the plane state check into the fbc functions
Instead of dealing with the presence/absence of the primary plane in the higher level pre/post plane update code let's move all that into the fbc code itself. Now the higher level code doesn't have to think about FBC details anymore. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191213133453.22152-3-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
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@ -6382,13 +6382,10 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_plane *primary = to_intel_plane(crtc->base.primary);
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const struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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const struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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const struct intel_plane_state *new_primary_state =
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intel_atomic_get_new_plane_state(state, primary);
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enum pipe pipe = crtc->pipe;
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intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
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@ -6399,8 +6396,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
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if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
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hsw_enable_ips(new_crtc_state);
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if (new_primary_state)
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intel_fbc_post_update(crtc);
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intel_fbc_post_update(state, crtc);
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if (needs_nv12_wa(old_crtc_state) &&
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!needs_nv12_wa(new_crtc_state))
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@ -6415,20 +6411,16 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_plane *primary = to_intel_plane(crtc->base.primary);
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const struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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const struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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const struct intel_plane_state *new_primary_state =
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intel_atomic_get_new_plane_state(state, primary);
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enum pipe pipe = crtc->pipe;
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if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
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hsw_disable_ips(old_crtc_state);
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if (new_primary_state &&
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intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state))
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if (intel_fbc_pre_update(state, crtc))
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intel_wait_for_vblank(dev_priv, pipe);
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/* Display WA 827 */
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@ -14857,9 +14849,6 @@ static void intel_update_crtc(struct intel_crtc *crtc,
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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bool modeset = needs_modeset(new_crtc_state);
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struct intel_plane_state *new_plane_state =
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intel_atomic_get_new_plane_state(state,
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to_intel_plane(crtc->base.primary));
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if (modeset) {
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intel_crtc_update_active_timings(new_crtc_state);
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@ -14882,8 +14871,8 @@ static void intel_update_crtc(struct intel_crtc *crtc,
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if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
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intel_fbc_disable(crtc);
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else if (new_plane_state)
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intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
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else
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intel_fbc_enable(state, crtc);
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/* Perform vblank evasion around commit operation */
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intel_pipe_update_start(new_crtc_state);
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@ -15045,15 +15034,12 @@ static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
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intel_atomic_get_new_crtc_state(state, crtc);
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struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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struct intel_plane_state *new_plane_state =
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intel_atomic_get_new_plane_state(state,
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to_intel_plane(crtc->base.primary));
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bool modeset = needs_modeset(new_crtc_state);
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if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
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intel_fbc_disable(crtc);
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else if (new_plane_state)
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intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
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else
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intel_fbc_enable(state, crtc);
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/* Perform vblank evasion around commit operation */
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intel_pipe_update_start(new_crtc_state);
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@ -867,10 +867,14 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
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return true;
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}
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bool intel_fbc_pre_update(struct intel_crtc *crtc,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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bool intel_fbc_pre_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct intel_plane *plane = to_intel_plane(crtc->base.primary);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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const struct intel_plane_state *plane_state =
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intel_atomic_get_new_plane_state(state, plane);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_fbc *fbc = &dev_priv->fbc;
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const char *reason = "update pending";
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@ -879,6 +883,9 @@ bool intel_fbc_pre_update(struct intel_crtc *crtc,
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if (!fbc_supported(dev_priv))
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return need_vblank_wait;
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if (!plane_state)
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return need_vblank_wait;
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mutex_lock(&fbc->lock);
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if (fbc->crtc != crtc)
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@ -967,14 +974,21 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc)
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intel_fbc_deactivate(dev_priv, "frontbuffer write");
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}
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void intel_fbc_post_update(struct intel_crtc *crtc)
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void intel_fbc_post_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_plane *plane = to_intel_plane(crtc->base.primary);
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const struct intel_plane_state *plane_state =
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intel_atomic_get_new_plane_state(state, plane);
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struct intel_fbc *fbc = &dev_priv->fbc;
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if (!fbc_supported(dev_priv))
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return;
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if (!plane_state)
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return;
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mutex_lock(&fbc->lock);
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__intel_fbc_post_update(crtc);
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mutex_unlock(&fbc->lock);
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@ -1107,18 +1121,24 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
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* intel_fbc_enable multiple times for the same pipe without an
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* intel_fbc_disable in the middle, as long as it is deactivated.
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*/
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void intel_fbc_enable(struct intel_crtc *crtc,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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void intel_fbc_enable(struct intel_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_plane *plane = to_intel_plane(crtc->base.primary);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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const struct intel_plane_state *plane_state =
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intel_atomic_get_new_plane_state(state, plane);
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struct intel_fbc *fbc = &dev_priv->fbc;
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struct intel_fbc_state_cache *cache = &fbc->state_cache;
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const struct drm_framebuffer *fb = plane_state->hw.fb;
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if (!fbc_supported(dev_priv))
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return;
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if (!plane_state)
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return;
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mutex_lock(&fbc->lock);
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if (fbc->crtc) {
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@ -1139,14 +1159,14 @@ void intel_fbc_enable(struct intel_crtc *crtc,
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if (intel_fbc_alloc_cfb(dev_priv,
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intel_fbc_calculate_cfb_size(dev_priv, cache),
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fb->format->cpp[0])) {
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plane_state->hw.fb->format->cpp[0])) {
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cache->plane.visible = false;
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fbc->no_fbc_reason = "not enough stolen memory";
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goto out;
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}
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if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) &&
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fb->modifier != I915_FORMAT_MOD_X_TILED)
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plane_state->hw.fb->modifier != I915_FORMAT_MOD_X_TILED)
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cache->gen9_wa_cfb_stride =
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DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
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else
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@ -19,14 +19,13 @@ struct intel_plane_state;
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void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
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struct intel_atomic_state *state);
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bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
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bool intel_fbc_pre_update(struct intel_crtc *crtc,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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void intel_fbc_post_update(struct intel_crtc *crtc);
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bool intel_fbc_pre_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_fbc_post_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_fbc_init(struct drm_i915_private *dev_priv);
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void intel_fbc_enable(struct intel_crtc *crtc,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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void intel_fbc_enable(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_fbc_disable(struct intel_crtc *crtc);
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void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
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void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
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