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drm/amd/powerplay: add is_dpm_running for SMU11
add is_dpm_running function to support smu s3 case. Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -483,6 +483,7 @@ struct smu_funcs
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int (*init_display)(struct smu_context *smu);
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int (*init_display)(struct smu_context *smu);
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int (*set_allowed_mask)(struct smu_context *smu);
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int (*set_allowed_mask)(struct smu_context *smu);
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int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
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int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
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bool (*is_dpm_running)(struct smu_context *smu);
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int (*enable_all_mask)(struct smu_context *smu);
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int (*enable_all_mask)(struct smu_context *smu);
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int (*disable_all_mask)(struct smu_context *smu);
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int (*disable_all_mask)(struct smu_context *smu);
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int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
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int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
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@ -608,6 +609,8 @@ struct smu_funcs
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((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
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((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
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#define smu_feature_get_enabled_mask(smu, mask, num) \
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#define smu_feature_get_enabled_mask(smu, mask, num) \
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((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
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((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
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#define smu_is_dpm_running(smu) \
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((smu)->funcs->is_dpm_running ? (smu)->funcs->is_dpm_running((smu)) : 0)
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#define smu_feature_enable_all(smu) \
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#define smu_feature_enable_all(smu) \
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((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
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((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
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#define smu_feature_disable_all(smu) \
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#define smu_feature_disable_all(smu) \
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@ -50,6 +50,16 @@ MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
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#define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
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#define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
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#define SMU11_VOLTAGE_SCALE 4
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#define SMU11_VOLTAGE_SCALE 4
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#define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
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FEATURE_DPM_GFXCLK_MASK | \
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FEATURE_DPM_UCLK_MASK | \
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FEATURE_DPM_SOCCLK_MASK | \
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FEATURE_DPM_UVD_MASK | \
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FEATURE_DPM_VCE_MASK | \
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FEATURE_DPM_MP0CLK_MASK | \
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FEATURE_DPM_LINK_MASK | \
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FEATURE_DPM_DCEFCLK_MASK)
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static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
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static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
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uint16_t msg)
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uint16_t msg)
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{
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{
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@ -750,6 +760,17 @@ static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
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return ret;
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return ret;
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}
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}
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static bool smu_v11_0_is_dpm_running(struct smu_context *smu)
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{
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int ret = 0;
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uint32_t feature_mask[2];
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unsigned long feature_enabled;
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ret = smu_v11_0_get_enabled_mask(smu, feature_mask, 2);
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feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
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((uint64_t)feature_mask[1] << 32));
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return !!(feature_enabled & SMC_DPM_FEATURE);
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}
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static int smu_v11_0_enable_all_mask(struct smu_context *smu)
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static int smu_v11_0_enable_all_mask(struct smu_context *smu)
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{
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{
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struct smu_feature *feature = &smu->smu_feature;
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struct smu_feature *feature = &smu->smu_feature;
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@ -1962,6 +1983,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
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.init_display = smu_v11_0_init_display,
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.init_display = smu_v11_0_init_display,
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.set_allowed_mask = smu_v11_0_set_allowed_mask,
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.set_allowed_mask = smu_v11_0_set_allowed_mask,
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.get_enabled_mask = smu_v11_0_get_enabled_mask,
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.get_enabled_mask = smu_v11_0_get_enabled_mask,
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.is_dpm_running = smu_v11_0_is_dpm_running,
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.enable_all_mask = smu_v11_0_enable_all_mask,
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.enable_all_mask = smu_v11_0_enable_all_mask,
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.disable_all_mask = smu_v11_0_disable_all_mask,
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.disable_all_mask = smu_v11_0_disable_all_mask,
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.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
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.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
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