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iio: make stm32 trigger driver use INDIO_HARDWARE_TRIGGERED mode
Add validate function to be use to use the correct trigger. Add an attribute to configure device mode like for quadrature and enable modes Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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@ -138,3 +138,18 @@ Description:
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Counting is enabled on rising edge of the connected
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trigger, and remains enabled for the duration of this
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selected mode.
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What: /sys/bus/iio/devices/iio:deviceX/in_count_trigger_mode_available
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KernelVersion: 4.13
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Contact: benjamin.gaignard@st.com
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Description:
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Reading returns the list possible trigger modes.
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What: /sys/bus/iio/devices/iio:deviceX/in_count0_trigger_mode
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KernelVersion: 4.13
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Contact: benjamin.gaignard@st.com
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Description:
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Configure the device counter trigger mode
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counting direction is set by in_count0_count_direction
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attribute and the counter is clocked by the connected trigger
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rising edges.
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@ -417,12 +417,70 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev,
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return -EINVAL;
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}
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static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
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struct iio_trigger *trig)
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{
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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const char * const *cur = priv->valids;
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unsigned int i = 0;
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if (!is_stm32_timer_trigger(trig))
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return -EINVAL;
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while (cur && *cur) {
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if (!strncmp(trig->name, *cur, strlen(trig->name))) {
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regmap_update_bits(priv->regmap,
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TIM_SMCR, TIM_SMCR_TS,
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i << TIM_SMCR_TS_SHIFT);
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return 0;
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}
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cur++;
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i++;
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}
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return -EINVAL;
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}
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static const struct iio_info stm32_trigger_info = {
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.driver_module = THIS_MODULE,
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.validate_trigger = stm32_counter_validate_trigger,
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.read_raw = stm32_counter_read_raw,
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.write_raw = stm32_counter_write_raw
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};
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static const char *const stm32_trigger_modes[] = {
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"trigger",
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};
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static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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unsigned int mode)
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{
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
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return 0;
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}
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static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan)
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{
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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u32 smcr;
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regmap_read(priv->regmap, TIM_SMCR, &smcr);
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return smcr == TIM_SMCR_SMS ? 0 : -EINVAL;
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}
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static const struct iio_enum stm32_trigger_mode_enum = {
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.items = stm32_trigger_modes,
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.num_items = ARRAY_SIZE(stm32_trigger_modes),
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.set = stm32_set_trigger_mode,
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.get = stm32_get_trigger_mode
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};
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static const char *const stm32_enable_modes[] = {
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"always",
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"gated",
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@ -606,6 +664,8 @@ static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
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IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum),
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IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
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IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum),
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IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
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IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum),
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{}
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};
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@ -630,6 +690,7 @@ static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev
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indio_dev->name = dev_name(dev);
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indio_dev->dev.parent = dev;
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indio_dev->info = &stm32_trigger_info;
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indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
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indio_dev->num_channels = 1;
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indio_dev->channels = &stm32_trigger_channel;
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indio_dev->dev.of_node = dev->of_node;
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