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dts: vt8500: Add ARM, AHB, APB and DDR clock nodes to SoC files

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Add support for the ARM, AHB, APB and DDR clocks found on the
WM8505, WM8650, WM8750 and WM8850 SoCs.

These clocks are gateable, but the enable part of the clock definition
is left out as there are no users for these clocks, and we don't want
them being disabled at boot, but it does provide users the ability to
check the current rate of these clocks.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
This commit is contained in:
Tony Prisk 2013-05-10 17:44:58 +12:00
parent 5c2b0a8531
commit 9e7b6d3eda
4 changed files with 92 additions and 8 deletions
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28
arch/arm/boot/dts/wm8505.dtsi
View File

@ -109,6 +109,34 @@ plld: plld {
reg = <0x20c>;
};
clkarm: arm {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&plla>;
divisor-reg = <0x300>;
};
clkahb: ahb {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x304>;
};
clkapb: apb {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x350>;
};
clkddr: ddr {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&plld>;
divisor-reg = <0x310>;
};
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";

37
arch/arm/boot/dts/wm8650.dtsi
View File

@ -113,6 +113,34 @@ plle: plle {
reg = <0x210>;
};
clkarm: arm {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&plla>;
divisor-reg = <0x300>;
};
clkahb: ahb {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x304>;
};
clkapb: apb {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x320>;
};
clkddr: ddr {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&plld>;
divisor-reg = <0x310>;
};
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
@ -129,14 +157,7 @@ clkuart1: uart1 {
enable-bit = <2>;
};
arm: arm {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&plla>;
divisor-reg = <0x300>;
};
sdhc: sdhc {
clksdhc: sdhc {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;

7
arch/arm/boot/dts/wm8750.dtsi
View File

@ -133,6 +133,13 @@ clkahb: ahb {
divisor-reg = <0x304>;
};
clkapb: apb {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x320>;
};
clkddr: ddr {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";

28
arch/arm/boot/dts/wm8850.dtsi
View File

@ -130,6 +130,34 @@ pllg: pllg {
reg = <0x218>;
};
clkarm: arm {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&plla>;
divisor-reg = <0x300>;
};
clkahb: ahb {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x304>;
};
clkapb: apb {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x320>;
};
clkddr: ddr {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&plld>;
divisor-reg = <0x310>;
};
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";