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drm/msm/dsi_pll_7nm: restore VCO rate during restore_state

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[ Upstream commit 5047ab95bb7db0e7b2ecfd5e9bcafc7fd822c652 ]

PHY disable/enable resets PLL registers to default values. Thus in
addition to restoring several registers we also need to restore VCO rate
settings.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 1ef7c99d14 ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2020-10-15 22:03:29 +03:00 committed by Greg Kroah-Hartman
parent cfc0c18403
commit 9e737d120b
1 changed files with 8 additions and 0 deletions
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8
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
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@ -585,6 +585,7 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll)
struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
u32 val;
int ret;
val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
val &= ~0x3;
@ -599,6 +600,13 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll)
val |= cached->pll_mux;
pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
if (ret) {
DRM_DEV_ERROR(&pll_7nm->pdev->dev,
"restore vco rate failed. ret=%d\n", ret);
return ret;
}
DBG("DSI PLL%d", pll_7nm->id);
return 0;