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drm/i915: FB backing gem obj should reside in LMEM

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If Local memory is supported by hardware, we want framebuffer backing
gem objects from local memory.

if the backing obj is not from LMEM, pin_to_display is failed.

v2:
  memory regions are correctly assigned to obj->memory_regions [tvrtko]
  migration failure is reported as debug log [Tvrtko]
v3:
  Migration is dropped. only error is reported [Daniel]
  mem region check is move to pin_to_display [Chris]
v4:
  s/dev_priv/i915 [chris]
v5:
  i915_gem_object_is_lmem is used for detecting the obj mem type. [Matt]

cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191105144414.30470-1-ramalingam.c@intel.com
This commit is contained in:
Ramalingam C 2019-11-05 20:14:14 +05:30 committed by Chris Wilson
parent 2b0a4fc25a
commit 9e678fc9ba
1 changed files with 7 additions and 1 deletions
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8
drivers/gpu/drm/i915/gem/i915_gem_domain.c
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@ -12,6 +12,7 @@
#include "i915_gem_ioctls.h" #include "i915_gem_ioctls.h"
#include "i915_gem_object.h" #include "i915_gem_object.h"
#include "i915_vma.h" #include "i915_vma.h"
#include "i915_gem_lmem.h"
static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj) static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
{ {
@ -419,11 +420,16 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
const struct i915_ggtt_view *view, const struct i915_ggtt_view *view,
unsigned int flags) unsigned int flags)
{ {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct i915_vma *vma; struct i915_vma *vma;
int ret; int ret;
assert_object_held(obj); assert_object_held(obj);
/* Frame buffer must be in LMEM (no migration yet) */
if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj))
return ERR_PTR(-EINVAL);
/* /*
* The display engine is not coherent with the LLC cache on gen6. As * The display engine is not coherent with the LLC cache on gen6. As
* a result, we make sure that the pinning that is about to occur is * a result, we make sure that the pinning that is about to occur is
@ -435,7 +441,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
* with that bit in the PTE to main memory with just one PIPE_CONTROL. * with that bit in the PTE to main memory with just one PIPE_CONTROL.
*/ */
ret = i915_gem_object_set_cache_level(obj, ret = i915_gem_object_set_cache_level(obj,
HAS_WT(to_i915(obj->base.dev)) ? HAS_WT(i915) ?
I915_CACHE_WT : I915_CACHE_NONE); I915_CACHE_WT : I915_CACHE_NONE);
if (ret) if (ret)
return ERR_PTR(ret); return ERR_PTR(ret);