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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 09:56:16 +07:00
drm/i915: Clean up HDMI deep color handling a bit
Reogranize the HDMI deep color state computation to just loop over possible bpc values. Avoids having to maintain so many variants of the clock etc. The current code also looks confused w.r.t. port_clock vs. bw_constrained. It would happily update port_clock for deep color but then not actually enable deep color due to bw_constrained being set. The new logic handles that case correctly. v2: Pull stuff into separate funcs (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190828183424.7856-1-ville.syrjala@linux.intel.com
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@ -2265,9 +2265,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
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static bool
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static bool
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intel_hdmi_ycbcr420_config(struct drm_connector *connector,
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intel_hdmi_ycbcr420_config(struct drm_connector *connector,
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struct intel_crtc_state *config,
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struct intel_crtc_state *config)
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int *clock_12bpc, int *clock_10bpc,
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int *clock_8bpc)
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{
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
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struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
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@ -2276,11 +2274,6 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
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return false;
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return false;
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}
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}
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/* YCBCR420 TMDS rate requirement is half the pixel clock */
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config->port_clock /= 2;
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*clock_12bpc /= 2;
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*clock_10bpc /= 2;
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*clock_8bpc /= 2;
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config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
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config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
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/* YCBCR 420 output conversion needs a scaler */
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/* YCBCR 420 output conversion needs a scaler */
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@ -2295,6 +2288,76 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
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return true;
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return true;
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}
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}
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static int intel_hdmi_port_clock(int clock, int bpc)
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{
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/*
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* Need to adjust the port link by:
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* 1.5x for 12bpc
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* 1.25x for 10bpc
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*/
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return clock * bpc / 8;
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}
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static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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int clock, bool force_dvi)
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{
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
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int bpc;
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for (bpc = 12; bpc >= 10; bpc -= 2) {
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if (hdmi_deep_color_possible(crtc_state, bpc) &&
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hdmi_port_clock_valid(intel_hdmi,
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intel_hdmi_port_clock(clock, bpc),
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true, force_dvi) == MODE_OK)
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return bpc;
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}
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return 8;
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}
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static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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bool force_dvi)
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{
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
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const struct drm_display_mode *adjusted_mode =
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&crtc_state->base.adjusted_mode;
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int bpc, clock = adjusted_mode->crtc_clock;
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
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clock *= 2;
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/* YCBCR420 TMDS rate requirement is half the pixel clock */
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if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
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clock /= 2;
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bpc = intel_hdmi_compute_bpc(encoder, crtc_state,
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clock, force_dvi);
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crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
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/*
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* pipe_bpp could already be below 8bpc due to
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* FDI bandwidth constraints. We shouldn't bump it
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* back up to 8bpc in that case.
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*/
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if (crtc_state->pipe_bpp > bpc * 3)
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crtc_state->pipe_bpp = bpc * 3;
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DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n",
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bpc, crtc_state->pipe_bpp);
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if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
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false, force_dvi) != MODE_OK) {
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DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n",
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crtc_state->port_clock);
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return -EINVAL;
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}
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return 0;
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}
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int intel_hdmi_compute_config(struct intel_encoder *encoder,
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int intel_hdmi_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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struct drm_connector_state *conn_state)
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@ -2306,11 +2369,8 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
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struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
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struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
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struct intel_digital_connector_state *intel_conn_state =
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struct intel_digital_connector_state *intel_conn_state =
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to_intel_digital_connector_state(conn_state);
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to_intel_digital_connector_state(conn_state);
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int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
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int clock_10bpc = clock_8bpc * 5 / 4;
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int clock_12bpc = clock_8bpc * 3 / 2;
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int desired_bpp;
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bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
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bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
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int ret;
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
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return -EINVAL;
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return -EINVAL;
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@ -2332,17 +2392,11 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
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intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
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intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
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}
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}
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
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pipe_config->pixel_multiplier = 2;
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pipe_config->pixel_multiplier = 2;
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clock_8bpc *= 2;
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clock_10bpc *= 2;
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clock_12bpc *= 2;
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}
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if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
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if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
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if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
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if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
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&clock_12bpc, &clock_10bpc,
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&clock_8bpc)) {
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DRM_ERROR("Can't support YCBCR420 output\n");
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DRM_ERROR("Can't support YCBCR420 output\n");
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -2359,43 +2413,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
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intel_conn_state->force_audio == HDMI_AUDIO_ON;
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intel_conn_state->force_audio == HDMI_AUDIO_ON;
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}
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}
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/*
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ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi);
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* Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
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if (ret)
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* to check that the higher clock still fits within limits.
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return ret;
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*/
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if (hdmi_deep_color_possible(pipe_config, 12) &&
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hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
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true, force_dvi) == MODE_OK) {
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DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
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desired_bpp = 12*3;
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/* Need to adjust the port link by 1.5x for 12bpc. */
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pipe_config->port_clock = clock_12bpc;
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} else if (hdmi_deep_color_possible(pipe_config, 10) &&
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hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
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true, force_dvi) == MODE_OK) {
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DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
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desired_bpp = 10 * 3;
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/* Need to adjust the port link by 1.25x for 10bpc. */
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pipe_config->port_clock = clock_10bpc;
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} else {
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DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
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desired_bpp = 8*3;
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pipe_config->port_clock = clock_8bpc;
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}
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if (!pipe_config->bw_constrained) {
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DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
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pipe_config->pipe_bpp = desired_bpp;
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}
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if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
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false, force_dvi) != MODE_OK) {
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DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
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return -EINVAL;
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}
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/* Set user selected PAR to incoming mode's member */
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/* Set user selected PAR to incoming mode's member */
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adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
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adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
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