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ASoC: arizona: Tidy up SYNCCLK selection and cache values
This patch caches the current SYNCCLK settings in the arizona_fll struct and uses these to simplify the code which determines which source should be used for the REFCLK and SYNCCLK inputs. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -1078,15 +1078,39 @@ int arizona_set_fll(struct arizona_fll *fll, int source,
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unsigned int Fref, unsigned int Fout)
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{
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struct arizona *arizona = fll->arizona;
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struct arizona_fll_cfg cfg, sync;
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struct arizona_fll_cfg ref, sync;
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unsigned int reg;
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int syncsrc;
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bool ena;
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int ret;
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if (fll->fref == Fref && fll->fout == Fout)
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return 0;
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if (fll->ref_src < 0 || fll->ref_src == source) {
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if (Fout) {
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ret = arizona_calc_fll(fll, &ref, Fref, Fout);
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if (ret != 0)
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return ret;
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}
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fll->sync_src = -1;
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fll->ref_src = source;
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fll->ref_freq = Fref;
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} else {
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if (Fout) {
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ret = arizona_calc_fll(fll, &ref, fll->ref_freq, Fout);
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if (ret != 0)
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return ret;
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ret = arizona_calc_fll(fll, &sync, Fref, Fout);
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if (ret != 0)
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return ret;
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}
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fll->sync_src = source;
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fll->sync_freq = Fref;
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}
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ret = regmap_read(arizona->regmap, fll->base + 1, ®);
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if (ret != 0) {
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arizona_fll_err(fll, "Failed to read current state: %d\n",
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@ -1096,24 +1120,32 @@ int arizona_set_fll(struct arizona_fll *fll, int source,
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ena = reg & ARIZONA_FLL1_ENA;
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if (Fout) {
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syncsrc = fll->ref_src;
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regmap_update_bits(arizona->regmap, fll->base + 5,
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ARIZONA_FLL1_OUTDIV_MASK,
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ref.outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
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if (source == syncsrc)
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syncsrc = -1;
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arizona_apply_fll(arizona, fll->base, &ref, fll->ref_src);
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if (fll->sync_src >= 0)
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arizona_apply_fll(arizona, fll->base + 0x10, &sync,
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fll->sync_src);
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if (syncsrc >= 0) {
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ret = arizona_calc_fll(fll, &sync, Fref, Fout);
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if (ret != 0)
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return ret;
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if (!ena)
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pm_runtime_get(arizona->dev);
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ret = arizona_calc_fll(fll, &cfg, fll->ref_freq, Fout);
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if (ret != 0)
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return ret;
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} else {
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ret = arizona_calc_fll(fll, &cfg, Fref, Fout);
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if (ret != 0)
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return ret;
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}
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/* Clear any pending completions */
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try_wait_for_completion(&fll->ok);
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regmap_update_bits(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
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if (fll->sync_src >= 0)
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regmap_update_bits(arizona->regmap, fll->base + 0x11,
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ARIZONA_FLL1_SYNC_ENA,
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ARIZONA_FLL1_SYNC_ENA);
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ret = wait_for_completion_timeout(&fll->ok,
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msecs_to_jiffies(250));
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if (ret == 0)
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arizona_fll_warn(fll, "Timed out waiting for lock\n");
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} else {
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regmap_update_bits(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_ENA, 0);
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@ -1122,42 +1154,8 @@ int arizona_set_fll(struct arizona_fll *fll, int source,
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if (ena)
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pm_runtime_put_autosuspend(arizona->dev);
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fll->fref = Fref;
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fll->fout = Fout;
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return 0;
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}
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regmap_update_bits(arizona->regmap, fll->base + 5,
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ARIZONA_FLL1_OUTDIV_MASK,
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cfg.outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
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if (syncsrc >= 0) {
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arizona_apply_fll(arizona, fll->base, &cfg, syncsrc);
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arizona_apply_fll(arizona, fll->base + 0x10, &sync, source);
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} else {
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arizona_apply_fll(arizona, fll->base, &cfg, source);
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}
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if (!ena)
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pm_runtime_get(arizona->dev);
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/* Clear any pending completions */
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try_wait_for_completion(&fll->ok);
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regmap_update_bits(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
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if (syncsrc >= 0)
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regmap_update_bits(arizona->regmap, fll->base + 0x11,
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ARIZONA_FLL1_SYNC_ENA,
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ARIZONA_FLL1_SYNC_ENA);
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ret = wait_for_completion_timeout(&fll->ok,
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msecs_to_jiffies(250));
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if (ret == 0)
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arizona_fll_warn(fll, "Timed out waiting for lock\n");
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fll->fref = Fref;
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fll->fout = Fout;
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@ -1176,6 +1174,7 @@ int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
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fll->id = id;
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fll->base = base;
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fll->arizona = arizona;
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fll->sync_src = -1;
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/* Configure default refclk to 32kHz if we have one */
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regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
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@ -201,6 +201,8 @@ struct arizona_fll {
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unsigned int fref;
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unsigned int fout;
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int sync_src;
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unsigned int sync_freq;
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int ref_src;
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unsigned int ref_freq;
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