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drm/i915: Modify DP set clock to accomodate more eDP timings v2
eDP 1.4 supports 4-5 extra link rates in additional to current 2 link rate. Create a structure to store the DPLL divisor data to improve readability. v2: Fix the gen4_dpll/pch_dpll initialization to C99 designated initializers, and use a single loop for all platforms. (Jani and Daniel) Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> [danvet: Fix up checkpatch warnings.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -38,6 +38,25 @@
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#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
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struct dp_link_dpll {
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int link_bw;
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struct dpll dpll;
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};
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static const struct dp_link_dpll gen4_dpll[] = {
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{ DP_LINK_BW_1_62,
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{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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{ DP_LINK_BW_2_7,
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{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
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};
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static const struct dp_link_dpll pch_dpll[] = {
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{ DP_LINK_BW_1_62,
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{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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{ DP_LINK_BW_2_7,
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{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
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};
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/**
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* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
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* @intel_dp: DP struct
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@ -649,42 +668,30 @@ intel_dp_set_clock(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config, int link_bw)
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{
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struct drm_device *dev = encoder->base.dev;
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const struct dp_link_dpll *divisor = NULL;
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int i, count = 0;
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if (IS_G4X(dev)) {
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if (link_bw == DP_LINK_BW_1_62) {
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pipe_config->dpll.p1 = 2;
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pipe_config->dpll.p2 = 10;
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pipe_config->dpll.n = 2;
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pipe_config->dpll.m1 = 23;
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pipe_config->dpll.m2 = 8;
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} else {
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pipe_config->dpll.p1 = 1;
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pipe_config->dpll.p2 = 10;
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pipe_config->dpll.n = 1;
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pipe_config->dpll.m1 = 14;
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pipe_config->dpll.m2 = 2;
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}
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pipe_config->clock_set = true;
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divisor = gen4_dpll;
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count = ARRAY_SIZE(gen4_dpll);
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} else if (IS_HASWELL(dev)) {
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/* Haswell has special-purpose DP DDI clocks. */
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} else if (HAS_PCH_SPLIT(dev)) {
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if (link_bw == DP_LINK_BW_1_62) {
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pipe_config->dpll.n = 1;
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pipe_config->dpll.p1 = 2;
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pipe_config->dpll.p2 = 10;
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pipe_config->dpll.m1 = 12;
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pipe_config->dpll.m2 = 9;
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} else {
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pipe_config->dpll.n = 2;
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pipe_config->dpll.p1 = 1;
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pipe_config->dpll.p2 = 10;
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pipe_config->dpll.m1 = 14;
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pipe_config->dpll.m2 = 8;
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}
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pipe_config->clock_set = true;
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divisor = pch_dpll;
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count = ARRAY_SIZE(pch_dpll);
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} else if (IS_VALLEYVIEW(dev)) {
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/* FIXME: Need to figure out optimized DP clocks for vlv. */
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}
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if (divisor && count) {
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for (i = 0; i < count; i++) {
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if (link_bw == divisor[i].link_bw) {
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pipe_config->dpll = divisor[i].dpll;
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pipe_config->clock_set = true;
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break;
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}
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}
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}
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}
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bool
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