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cxl: Remove racy attempt to force EEH invocation in reset
cxl_reset currently PERSTs the slot, and then repeatedly tries to
read MMIO space in order to kick off EEH.
There are 2 problems with this: it's unnecessary, and it's racy.
It's unnecessary because the PERST will bring down the PHB link.
That will be picked up by the CAPP, which will send out an HMI.
Skiboot, noticing an HMI from the CAPP, will send an OPAL
notification to the kernel, which will trigger EEH recovery.
It's also racy: the EEH recovery triggered by the CAPP will
eventually cause the MMIO space to have its mapping invalidated
and the pointer NULLed out. This races with our attempt to read
the MMIO space. This is causing OOPSes in testing.
Simply drop all the attempts to force EEH detection, and trust
that Skiboot will send the notification and that we'll act on it.
The Skiboot code to send the EEH notification has been in Skiboot
for as long as CAPP recovery has been supported, so we don't need
to worry about breaking obscure setups with ancient firmware.
Cc: Ryan Grimm <grimm@linux.vnet.ibm.com>
Cc: stable@vger.kernel.org
Fixes: 62fa19d4b4
("cxl: Add ability to reset the card")
Signed-off-by: Daniel Axtens <dja@axtens.net>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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parent
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@ -876,8 +876,6 @@ int cxl_reset(struct cxl *adapter)
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{
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struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
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int rc;
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int i;
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u32 val;
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if (adapter->perst_same_image) {
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dev_warn(&dev->dev,
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@ -895,20 +893,6 @@ int cxl_reset(struct cxl *adapter)
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return rc;
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}
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/* the PERST done above fences the PHB. So, reset depends on EEH
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* to unbind the driver, tell Sapphire to reinit the PHB, and rebind
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* the driver. Do an mmio read explictly to ensure EEH notices the
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* fenced PHB. Retry for a few seconds before giving up. */
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i = 0;
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while (((val = mmio_read32be(adapter->p1_mmio)) != 0xffffffff) &&
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(i < 5)) {
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msleep(500);
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i++;
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}
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if (val != 0xffffffff)
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dev_err(&dev->dev, "cxl: PERST failed to trigger EEH\n");
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return rc;
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}
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