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arm64: dts: meson-axg: add initial A113D SoC DT support
Try to add basic DT support for the Amlogic's Meson-AXG A113D SoC, which describe components as follows: Reserve Memory, CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Yixun Lan
Kevin Hilman
parent
1000cec2f0
commit
9d59b70850
@ -1,3 +1,4 @@
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dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
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22
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
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22
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
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/*
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* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/dts-v1/;
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#include "meson-axg.dtsi"
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/ {
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compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
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model = "Amlogic Meson AXG S400 Development Board";
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aliases {
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serial0 = &uart_AO;
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};
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};
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&uart_AO {
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status = "okay";
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};
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204
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
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204
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
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/*
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* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "amlogic,meson-axg";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 16 MiB reserved for Hardware ROM Firmware */
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hwrom_reserved: hwrom@0 {
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reg = <0x0 0x0 0x0 0x1000000>;
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no-map;
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};
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/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@05000000 {
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reg = <0x0 0x05000000 0x0 0x300000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
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};
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xtal: xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cbus: cbus@ffd00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffd00000 0x0 0x25000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
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uart_A: serial@24000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
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reg = <0x0 0x24000 0x0 0x14>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart_B: serial@23000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
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reg = <0x0 0x23000 0x0 0x14>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xffc01000 0 0x1000>,
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<0x0 0xffc02000 0 0x2000>,
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<0x0 0xffc04000 0 0x2000>,
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<0x0 0xffc06000 0 0x2000>;
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interrupt-controller;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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};
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mailbox: mailbox@ff63dc00 {
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compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
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reg = <0 0xff63dc00 0 0x400>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
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#mbox-cells = <1>;
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};
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sram: sram@fffc0000 {
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compatible = "amlogic,meson-axg-sram", "mmio-sram";
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reg = <0x0 0xfffc0000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0xfffc0000 0x20000>;
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cpu_scp_lpri: scp-shmem@0 {
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compatible = "amlogic,meson-axg-scp-shmem";
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reg = <0x13000 0x400>;
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};
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cpu_scp_hpri: scp-shmem@200 {
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compatible = "amlogic,meson-axg-scp-shmem";
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reg = <0x13400 0x400>;
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};
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};
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aobus: aobus@ff800000 {
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compatible = "simple-bus";
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reg = <0x0 0xff800000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
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uart_AO: serial@3000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x3000 0x0 0x18>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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uart_AO_B: serial@4000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x4000 0x0 0x18>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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};
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};
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};
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