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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)
Re-parenting to intermediate clock is supported now by the clock driver and thus there is no need in a customized CPUFreq driver, all that code is common for both Tegra20 and Tegra30. The available CPU freqs are now specified in device-tree in a form of OPPs, all users should update their device-trees. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko
Thierry Reding
parent
8f3d9f3542
commit
9ce2746304
@ -295,11 +295,11 @@ config ARM_TANGO_CPUFREQ
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default y
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config ARM_TEGRA20_CPUFREQ
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tristate "Tegra20 CPUFreq support"
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depends on ARCH_TEGRA
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tristate "Tegra20/30 CPUFreq support"
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depends on ARCH_TEGRA && CPUFREQ_DT
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default y
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help
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This adds the CPUFreq driver support for Tegra20 SOCs.
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This adds the CPUFreq driver support for Tegra20/30 SOCs.
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config ARM_TEGRA124_CPUFREQ
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bool "Tegra124 CPUFreq support"
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@ -7,201 +7,96 @@
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* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
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*/
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/bits.h>
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/types.h>
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static struct cpufreq_frequency_table freq_table[] = {
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{ .frequency = 216000 },
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{ .frequency = 312000 },
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{ .frequency = 456000 },
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{ .frequency = 608000 },
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{ .frequency = 760000 },
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{ .frequency = 816000 },
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{ .frequency = 912000 },
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{ .frequency = 1000000 },
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{ .frequency = CPUFREQ_TABLE_END },
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};
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#include <soc/tegra/common.h>
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#include <soc/tegra/fuse.h>
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struct tegra20_cpufreq {
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struct device *dev;
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struct cpufreq_driver driver;
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struct clk *cpu_clk;
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struct clk *pll_x_clk;
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struct clk *pll_p_clk;
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bool pll_x_prepared;
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};
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static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
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unsigned int index)
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static bool cpu0_node_has_opp_v2_prop(void)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000;
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struct device_node *np = of_cpu_device_node_get(0);
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bool ret = false;
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/*
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* Don't switch to intermediate freq if:
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* - we are already at it, i.e. policy->cur == ifreq
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* - index corresponds to ifreq
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*/
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if (freq_table[index].frequency == ifreq || policy->cur == ifreq)
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return 0;
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return ifreq;
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}
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static int tegra_target_intermediate(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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int ret;
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/*
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* Take an extra reference to the main pll so it doesn't turn
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* off when we move the cpu off of it as enabling it again while we
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* switch to it from tegra_target() would take additional time.
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*
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* When target-freq is equal to intermediate freq we don't need to
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* switch to an intermediate freq and so this routine isn't called.
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* Also, we wouldn't be using pll_x anymore and must not take extra
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* reference to it, as it can be disabled now to save some power.
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*/
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clk_prepare_enable(cpufreq->pll_x_clk);
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ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk);
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if (ret)
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clk_disable_unprepare(cpufreq->pll_x_clk);
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else
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cpufreq->pll_x_prepared = true;
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if (of_get_property(np, "operating-points-v2", NULL))
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ret = true;
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of_node_put(np);
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return ret;
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}
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static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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unsigned long rate = freq_table[index].frequency;
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unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000;
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int ret;
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/*
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* target freq == pll_p, don't need to take extra reference to pll_x_clk
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* as it isn't used anymore.
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*/
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if (rate == ifreq)
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return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk);
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ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000);
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/* Restore to earlier frequency on error, i.e. pll_x */
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if (ret)
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dev_err(cpufreq->dev, "Failed to change pll_x to %lu\n", rate);
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ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk);
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/* This shouldn't fail while changing or restoring */
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WARN_ON(ret);
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/*
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* Drop count to pll_x clock only if we switched to intermediate freq
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* earlier while transitioning to a target frequency.
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*/
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if (cpufreq->pll_x_prepared) {
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clk_disable_unprepare(cpufreq->pll_x_clk);
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cpufreq->pll_x_prepared = false;
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}
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return ret;
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}
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static int tegra_cpu_init(struct cpufreq_policy *policy)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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clk_prepare_enable(cpufreq->cpu_clk);
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/* FIXME: what's the actual transition time? */
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cpufreq_generic_init(policy, freq_table, 300 * 1000);
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policy->clk = cpufreq->cpu_clk;
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policy->suspend_freq = freq_table[0].frequency;
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return 0;
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}
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static int tegra_cpu_exit(struct cpufreq_policy *policy)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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clk_disable_unprepare(cpufreq->cpu_clk);
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return 0;
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}
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static int tegra20_cpufreq_probe(struct platform_device *pdev)
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{
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struct tegra20_cpufreq *cpufreq;
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struct platform_device *cpufreq_dt;
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struct opp_table *opp_table;
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struct device *cpu_dev;
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u32 versions[2];
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int err;
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cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL);
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if (!cpufreq)
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return -ENOMEM;
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cpufreq->cpu_clk = clk_get_sys(NULL, "cclk");
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if (IS_ERR(cpufreq->cpu_clk))
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return PTR_ERR(cpufreq->cpu_clk);
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cpufreq->pll_x_clk = clk_get_sys(NULL, "pll_x");
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if (IS_ERR(cpufreq->pll_x_clk)) {
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err = PTR_ERR(cpufreq->pll_x_clk);
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goto put_cpu;
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if (!cpu0_node_has_opp_v2_prop()) {
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dev_err(&pdev->dev, "operating points not found\n");
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dev_err(&pdev->dev, "please update your device tree\n");
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return -ENODEV;
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}
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cpufreq->pll_p_clk = clk_get_sys(NULL, "pll_p");
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if (IS_ERR(cpufreq->pll_p_clk)) {
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err = PTR_ERR(cpufreq->pll_p_clk);
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goto put_pll_x;
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if (of_machine_is_compatible("nvidia,tegra20")) {
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versions[0] = BIT(tegra_sku_info.cpu_process_id);
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versions[1] = BIT(tegra_sku_info.soc_speedo_id);
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} else {
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versions[0] = BIT(tegra_sku_info.cpu_process_id);
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versions[1] = BIT(tegra_sku_info.cpu_speedo_id);
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}
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cpufreq->dev = &pdev->dev;
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cpufreq->driver.get = cpufreq_generic_get;
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cpufreq->driver.attr = cpufreq_generic_attr;
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cpufreq->driver.init = tegra_cpu_init;
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cpufreq->driver.exit = tegra_cpu_exit;
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cpufreq->driver.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK;
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cpufreq->driver.verify = cpufreq_generic_frequency_table_verify;
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cpufreq->driver.suspend = cpufreq_generic_suspend;
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cpufreq->driver.driver_data = cpufreq;
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cpufreq->driver.target_index = tegra_target;
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cpufreq->driver.get_intermediate = tegra_get_intermediate;
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cpufreq->driver.target_intermediate = tegra_target_intermediate;
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snprintf(cpufreq->driver.name, CPUFREQ_NAME_LEN, "tegra");
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dev_info(&pdev->dev, "hardware version 0x%x 0x%x\n",
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versions[0], versions[1]);
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err = cpufreq_register_driver(&cpufreq->driver);
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if (err)
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goto put_pll_p;
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cpu_dev = get_cpu_device(0);
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if (WARN_ON(!cpu_dev))
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return -ENODEV;
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platform_set_drvdata(pdev, cpufreq);
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opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2);
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err = PTR_ERR_OR_ZERO(opp_table);
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if (err) {
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dev_err(&pdev->dev, "failed to set supported hw: %d\n", err);
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return err;
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}
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cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
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err = PTR_ERR_OR_ZERO(cpufreq_dt);
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if (err) {
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dev_err(&pdev->dev,
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"failed to create cpufreq-dt device: %d\n", err);
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goto err_put_supported_hw;
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}
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platform_set_drvdata(pdev, cpufreq_dt);
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return 0;
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put_pll_p:
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clk_put(cpufreq->pll_p_clk);
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put_pll_x:
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clk_put(cpufreq->pll_x_clk);
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put_cpu:
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clk_put(cpufreq->cpu_clk);
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err_put_supported_hw:
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dev_pm_opp_put_supported_hw(opp_table);
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return err;
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}
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static int tegra20_cpufreq_remove(struct platform_device *pdev)
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{
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struct tegra20_cpufreq *cpufreq = platform_get_drvdata(pdev);
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struct platform_device *cpufreq_dt;
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struct opp_table *opp_table;
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cpufreq_unregister_driver(&cpufreq->driver);
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cpufreq_dt = platform_get_drvdata(pdev);
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platform_device_unregister(cpufreq_dt);
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clk_put(cpufreq->pll_p_clk);
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clk_put(cpufreq->pll_x_clk);
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clk_put(cpufreq->cpu_clk);
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opp_table = dev_pm_opp_get_opp_table(get_cpu_device(0));
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dev_pm_opp_put_supported_hw(opp_table);
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dev_pm_opp_put_opp_table(opp_table);
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return 0;
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}
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