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drm/amdgpu:enable mcbp for gfx9(v2)

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set bit 21 of IB.control filed to actually enable
MCBP for SRIOV
v2:
add flag for preemption enable bit for soc15 and use
this flag instead of hardcode.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Monk Liu 2017-03-21 11:50:43 +08:00 committed by Alex Deucher
parent 806ba2d4f5
commit 9ccd52eb24
2 changed files with 4 additions and 0 deletions
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3
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@ -3073,6 +3073,9 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
control |= ib->length_dw | (vm_id << 24); control |= ib->length_dw | (vm_id << 24);
if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
control |= INDIRECT_BUFFER_PRE_ENB(1);
amdgpu_ring_write(ring, header); amdgpu_ring_write(ring, header);
BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
amdgpu_ring_write(ring, amdgpu_ring_write(ring,

1
drivers/gpu/drm/amd/amdgpu/soc15d.h
View File

@ -137,6 +137,7 @@
* 1 - Stream * 1 - Stream
* 2 - Bypass * 2 - Bypass
*/ */
#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)
#define PACKET3_COPY_DATA 0x40 #define PACKET3_COPY_DATA 0x40
#define PACKET3_PFP_SYNC_ME 0x42 #define PACKET3_PFP_SYNC_ME 0x42
#define PACKET3_COND_WRITE 0x45 #define PACKET3_COND_WRITE 0x45