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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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usb: musb: tusb6010_omap: Convert to DMAengine API
With the port_window support in DMAengine and the sDMA driver we can convert the driver to DMAengine. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Peter Ujfalusi
Greg Kroah-Hartman
parent
868772d89d
commit
9c691cc9f8
@ -15,7 +15,7 @@
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/omap-dma.h>
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#include <linux/dmaengine.h>
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#include "musb_core.h"
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#include "tusb6010.h"
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@ -24,17 +24,9 @@
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#define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
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#define OMAP24XX_DMA_EXT_DMAREQ0 2
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#define OMAP24XX_DMA_EXT_DMAREQ1 3
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#define OMAP242X_DMA_EXT_DMAREQ2 14
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#define OMAP242X_DMA_EXT_DMAREQ3 15
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#define OMAP242X_DMA_EXT_DMAREQ4 16
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#define OMAP242X_DMA_EXT_DMAREQ5 64
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struct tusb_dma_data {
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int ch;
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s8 dmareq;
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s8 sync_dev;
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struct dma_chan *chan;
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};
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struct tusb_omap_dma_ch {
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@ -105,7 +97,7 @@ static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
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* See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
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* musb_gadget.c.
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*/
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static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
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static void tusb_omap_dma_cb(void *data)
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{
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struct dma_channel *channel = (struct dma_channel *)data;
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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@ -116,18 +108,11 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
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void __iomem *ep_conf = hw_ep->conf;
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void __iomem *mbase = musb->mregs;
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unsigned long remaining, flags, pio;
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int ch;
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spin_lock_irqsave(&musb->lock, flags);
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ch = chdat->dma_data->ch;
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if (ch_status != OMAP_DMA_BLOCK_IRQ)
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printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
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dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
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chdat->epnum, chdat->tx ? "tx" : "rx",
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ch, ch_status);
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dev_dbg(musb->controller, "ep%i %s dma callback\n",
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chdat->epnum, chdat->tx ? "tx" : "rx");
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if (chdat->tx)
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remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
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@ -138,8 +123,8 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
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/* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
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if (unlikely(remaining > chdat->transfer_len)) {
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dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
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chdat->tx ? "tx" : "rx", ch, remaining);
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dev_dbg(musb->controller, "Corrupt %s XFR_SIZE: 0x%08lx\n",
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chdat->tx ? "tx" : "rx", remaining);
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remaining = 0;
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}
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@ -206,13 +191,16 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
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struct musb_hw_ep *hw_ep = chdat->hw_ep;
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void __iomem *mbase = musb->mregs;
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void __iomem *ep_conf = hw_ep->conf;
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dma_addr_t fifo = hw_ep->fifo_sync;
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struct omap_dma_channel_params dma_params;
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dma_addr_t fifo_addr = hw_ep->fifo_sync;
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u32 dma_remaining;
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int src_burst, dst_burst;
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u16 csr;
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u32 psize;
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struct tusb_dma_data *dma_data;
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struct dma_async_tx_descriptor *dma_desc;
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struct dma_slave_config dma_cfg;
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enum dma_transfer_direction dma_dir;
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u32 port_window;
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int ret;
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if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
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return false;
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@ -238,10 +226,8 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
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dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
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if (dma_remaining) {
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dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
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chdat->tx ? "tx" : "rx",
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chdat->dma_data ? chdat->dma_data->ch : -1,
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dma_remaining);
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dev_dbg(musb->controller, "Busy %s dma, not using: %08x\n",
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chdat->tx ? "tx" : "rx", dma_remaining);
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return false;
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}
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@ -258,7 +244,7 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
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dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
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return false;
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}
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if (dma_data->ch < 0) {
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if (dma_data->dmareq < 0) {
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/* REVISIT: This should get blocked earlier, happens
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* with MSC ErrorRecoveryTest
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*/
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@ -267,8 +253,6 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
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}
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}
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omap_set_dma_callback(dma_data->ch, tusb_omap_dma_cb, channel);
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chdat->packet_sz = packet_sz;
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chdat->len = len;
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channel->actual_len = 0;
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@ -276,79 +260,68 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
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channel->status = MUSB_DMA_STATUS_BUSY;
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/* Since we're recycling dma areas, we need to clean or invalidate */
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if (chdat->tx)
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if (chdat->tx) {
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dma_dir = DMA_MEM_TO_DEV;
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dma_map_single(dev, phys_to_virt(dma_addr), len,
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DMA_TO_DEVICE);
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else
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} else {
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dma_dir = DMA_DEV_TO_MEM;
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dma_map_single(dev, phys_to_virt(dma_addr), len,
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DMA_FROM_DEVICE);
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}
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memset(&dma_cfg, 0, sizeof(dma_cfg));
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/* Use 16-bit transfer if dma_addr is not 32-bit aligned */
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if ((dma_addr & 0x3) == 0) {
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dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
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dma_params.elem_count = 8; /* Elements in frame */
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dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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port_window = 8;
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} else {
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dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
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dma_params.elem_count = 16; /* Elements in frame */
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fifo = hw_ep->fifo_async;
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dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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port_window = 16;
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fifo_addr = hw_ep->fifo_async;
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}
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dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
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dev_dbg(musb->controller,
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"ep%i %s dma: %pad len: %u(%u) packet_sz: %i(%i)\n",
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chdat->epnum, chdat->tx ? "tx" : "rx", &dma_addr,
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chdat->transfer_len, len, chdat->transfer_packet_sz, packet_sz);
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dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %pad len: %u(%u) packet_sz: %i(%i)\n",
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chdat->epnum, chdat->tx ? "tx" : "rx",
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dma_data->ch, &dma_addr, chdat->transfer_len, len,
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chdat->transfer_packet_sz, packet_sz);
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dma_cfg.src_addr = fifo_addr;
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dma_cfg.dst_addr = fifo_addr;
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dma_cfg.src_port_window_size = port_window;
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dma_cfg.src_maxburst = port_window;
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dma_cfg.dst_port_window_size = port_window;
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dma_cfg.dst_maxburst = port_window;
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/*
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* Prepare omap DMA for transfer
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*/
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if (chdat->tx) {
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dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
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dma_params.src_start = (unsigned long)dma_addr;
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dma_params.src_ei = 0;
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dma_params.src_fi = 0;
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dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
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dma_params.dst_start = (unsigned long)fifo;
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dma_params.dst_ei = 1;
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dma_params.dst_fi = -31; /* Loop 32 byte window */
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dma_params.trigger = dma_data->sync_dev;
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dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
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dma_params.src_or_dst_synch = 0; /* Dest sync */
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src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */
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dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */
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} else {
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dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
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dma_params.src_start = (unsigned long)fifo;
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dma_params.src_ei = 1;
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dma_params.src_fi = -31; /* Loop 32 byte window */
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dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
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dma_params.dst_start = (unsigned long)dma_addr;
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dma_params.dst_ei = 0;
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dma_params.dst_fi = 0;
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dma_params.trigger = dma_data->sync_dev;
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dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
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dma_params.src_or_dst_synch = 1; /* Source sync */
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src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */
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dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
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ret = dmaengine_slave_config(dma_data->chan, &dma_cfg);
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if (ret) {
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dev_err(musb->controller, "DMA slave config failed: %d\n", ret);
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return false;
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}
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dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
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dma_desc = dmaengine_prep_slave_single(dma_data->chan, dma_addr,
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chdat->transfer_len, dma_dir,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma_desc) {
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dev_err(musb->controller, "DMA prep_slave_single failed\n");
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return false;
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}
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dma_desc->callback = tusb_omap_dma_cb;
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dma_desc->callback_param = channel;
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dmaengine_submit(dma_desc);
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dev_dbg(musb->controller,
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"ep%i %s using %i-bit %s dma from %pad to %pad\n",
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chdat->epnum, chdat->tx ? "tx" : "rx",
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(dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
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dma_cfg.src_addr_width * 8,
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((dma_addr & 0x3) == 0) ? "sync" : "async",
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dma_params.src_start, dma_params.dst_start);
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omap_set_dma_params(dma_data->ch, &dma_params);
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omap_set_dma_src_burst_mode(dma_data->ch, src_burst);
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omap_set_dma_dest_burst_mode(dma_data->ch, dst_burst);
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omap_set_dma_write_mode(dma_data->ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
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(dma_dir == DMA_MEM_TO_DEV) ? &dma_addr : &fifo_addr,
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(dma_dir == DMA_MEM_TO_DEV) ? &fifo_addr : &dma_addr);
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/*
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* Prepare MUSB for DMA transfer
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@ -368,10 +341,8 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
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csr | MUSB_RXCSR_P_WZC_BITS);
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}
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/*
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* Start DMA transfer
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*/
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omap_start_dma(dma_data->ch);
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/* Start DMA transfer */
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dma_async_issue_pending(dma_data->chan);
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if (chdat->tx) {
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/* Send transfer_packet_sz packets at a time */
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@ -401,7 +372,7 @@ static int tusb_omap_dma_abort(struct dma_channel *channel)
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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if (chdat->dma_data)
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omap_stop_dma(chdat->dma_data->ch);
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dmaengine_terminate_all(chdat->dma_data->chan);
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channel->status = MUSB_DMA_STATUS_FREE;
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@ -511,11 +482,11 @@ tusb_omap_dma_allocate(struct dma_controller *c,
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dma_data = chdat->dma_data;
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dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
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dev_dbg(musb->controller, "ep%i %s dma: %s dmareq%i\n",
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chdat->epnum,
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chdat->tx ? "tx" : "rx",
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tusb_dma->multichannel ? "shared" : "dedicated",
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dma_data->ch, dma_data->dmareq, dma_data->sync_dev);
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dma_data->dmareq);
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return channel;
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@ -533,12 +504,11 @@ static void tusb_omap_dma_release(struct dma_channel *channel)
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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struct musb *musb = chdat->musb;
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dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum,
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chdat->dma_data->ch);
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dev_dbg(musb->controller, "Release for ep%i\n", chdat->epnum);
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channel->status = MUSB_DMA_STATUS_UNKNOWN;
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omap_stop_dma(chdat->dma_data->ch);
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dmaengine_terminate_sync(chdat->dma_data->chan);
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tusb_omap_dma_free_dmareq(chdat);
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channel = NULL;
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@ -558,8 +528,8 @@ void tusb_dma_controller_destroy(struct dma_controller *c)
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}
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/* Free up the DMA channels */
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if (tusb_dma && tusb_dma->dma_pool[i].ch >= 0)
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omap_free_dma(tusb_dma->dma_pool[i].ch);
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if (tusb_dma && tusb_dma->dma_pool[i].chan)
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dma_release_channel(tusb_dma->dma_pool[i].chan);
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}
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kfree(tusb_dma);
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@ -568,16 +538,9 @@ EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy);
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static int tusb_omap_allocate_dma_pool(struct tusb_omap_dma *tusb_dma)
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{
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struct musb *musb = tusb_dma->controller.musb;
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int i;
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int ret = 0;
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const int sync_dev[6] = {
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OMAP24XX_DMA_EXT_DMAREQ0,
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OMAP24XX_DMA_EXT_DMAREQ1,
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OMAP242X_DMA_EXT_DMAREQ2,
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OMAP242X_DMA_EXT_DMAREQ3,
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OMAP242X_DMA_EXT_DMAREQ4,
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OMAP242X_DMA_EXT_DMAREQ5,
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};
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for (i = 0; i < MAX_DMAREQ; i++) {
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struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
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@ -591,22 +554,18 @@ static int tusb_omap_allocate_dma_pool(struct tusb_omap_dma *tusb_dma)
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char ch_name[8];
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sprintf(ch_name, "dmareq%d", i);
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dma_data->sync_dev = sync_dev[i];
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dma_data->ch = -1;
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/* callback data is ngoing to be set later */
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ret = omap_request_dma(dma_data->sync_dev, ch_name,
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tusb_omap_dma_cb, NULL, &dma_data->ch);
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if (ret != 0) {
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dev_err(tusb_dma->controller.musb->controller,
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dma_data->chan = dma_request_chan(musb->controller,
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ch_name);
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if (IS_ERR(dma_data->chan)) {
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dev_err(musb->controller,
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"Failed to request %s\n", ch_name);
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ret = PTR_ERR(dma_data->chan);
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goto dma_error;
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}
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dma_data->dmareq = i;
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} else {
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dma_data->dmareq = -1;
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dma_data->sync_dev = -1;
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dma_data->ch = -1;
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}
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}
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@ -616,8 +575,8 @@ static int tusb_omap_allocate_dma_pool(struct tusb_omap_dma *tusb_dma)
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for (; i >= 0; i--) {
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struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
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if (dma_data->ch >= 0)
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omap_free_dma(dma_data->ch);
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if (dma_data->dmareq >= 0)
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dma_release_channel(dma_data->chan);
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}
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return ret;
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