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drm/amdgpu/uvd3.x: fix register definition warnings

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drop the duplicate register macros from sid.h and use the
standard ones in the oss register headers.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2020-06-22 18:10:36 -04:00
parent 8c823e4ff6
commit 9c39d77c07
3 changed files with 3 additions and 19 deletions
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1
drivers/gpu/drm/amd/amdgpu/si.c
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@ -44,6 +44,7 @@
#include "dce_virtual.h"
#include "gca/gfx_6_0_d.h"
#include "oss/oss_1_0_d.h"
#include "oss/oss_1_0_sh_mask.h"
#include "gmc/gmc_6_0_d.h"
#include "dce/dce_6_0_d.h"
#include "uvd/uvd_4_0_d.h"

2
drivers/gpu/drm/amd/amdgpu/si_ih.c
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@ -27,6 +27,8 @@
#include "amdgpu_ih.h"
#include "sid.h"
#include "si_ih.h"
#include "oss/oss_1_0_d.h"
#include "oss/oss_1_0_sh_mask.h"
static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);

19
drivers/gpu/drm/amd/amdgpu/sid.h
View File

@ -2340,11 +2340,6 @@
# define NI_INPUT_GAMMA_XVYCC_222 3
# define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)
#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
#define SRBM_STATUS__IH_BUSY_MASK 0x20000
#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
#define BLACKOUT_MODE_MASK 0x00000007
#define VGA_RENDER_CONTROL 0xC0
#define R_000300_VGA_RENDER_CONTROL 0xC0
@ -2431,18 +2426,6 @@
#define MC_SEQ_MISC0__MT__HBM 0x60000000
#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
#define SRBM_STATUS__MCB_BUSY_MASK 0x200
#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
#define SRBM_STATUS__MCC_BUSY_MASK 0x800
#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
#define SRBM_STATUS__VMC_BUSY_MASK 0x100
#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
#define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
@ -2467,8 +2450,6 @@
#define PCIE_BUS_CLK 10000
#define TCLK (PCIE_BUS_CLK / 10)
#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
#define PCIE_PORT_INDEX 0xe
#define PCIE_PORT_DATA 0xf
#define EVERGREEN_PIF_PHY0_INDEX 0x8