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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-12 17:26:44 +07:00
igc: Add dump options
Placeholder for debugging functionality. In this patch, we add some registers and rings summary dumps. Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Sasha Neftin
Jeff Kirsher
parent
8594a7f384
commit
9c384ee31e
@ -8,4 +8,4 @@
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obj-$(CONFIG_IGC) += igc.o
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igc-objs := igc_main.o igc_mac.o igc_i225.o igc_base.o igc_nvm.o igc_phy.o \
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igc_ethtool.o igc_ptp.o
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igc_ethtool.o igc_ptp.o igc_dump.o
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@ -42,6 +42,10 @@ int igc_del_mac_steering_filter(struct igc_adapter *adapter,
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const u8 *addr, u8 queue, u8 flags);
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void igc_update_stats(struct igc_adapter *adapter);
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/* igc_dump declarations */
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void igc_rings_dump(struct igc_adapter *adapter);
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void igc_regs_dump(struct igc_adapter *adapter);
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extern char igc_driver_name[];
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extern char igc_driver_version[];
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@ -259,6 +259,9 @@
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#define IGC_GPIE_EIAME 0x40000000
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#define IGC_GPIE_PBA 0x80000000
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/* Receive Descriptor bit definitions */
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#define IGC_RXD_STAT_DD 0x01 /* Descriptor Done */
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/* Transmit Descriptor bit definitions */
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#define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */
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#define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */
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323
drivers/net/ethernet/intel/igc/igc_dump.c
Normal file
323
drivers/net/ethernet/intel/igc/igc_dump.c
Normal file
@ -0,0 +1,323 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2018 Intel Corporation */
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#include "igc.h"
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struct igc_reg_info {
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u32 ofs;
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char *name;
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};
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static const struct igc_reg_info igc_reg_info_tbl[] = {
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/* General Registers */
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{IGC_CTRL, "CTRL"},
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{IGC_STATUS, "STATUS"},
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{IGC_CTRL_EXT, "CTRL_EXT"},
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{IGC_MDIC, "MDIC"},
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/* Interrupt Registers */
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{IGC_ICR, "ICR"},
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/* RX Registers */
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{IGC_RCTL, "RCTL"},
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{IGC_RDLEN(0), "RDLEN"},
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{IGC_RDH(0), "RDH"},
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{IGC_RDT(0), "RDT"},
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{IGC_RXDCTL(0), "RXDCTL"},
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{IGC_RDBAL(0), "RDBAL"},
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{IGC_RDBAH(0), "RDBAH"},
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/* TX Registers */
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{IGC_TCTL, "TCTL"},
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{IGC_TDBAL(0), "TDBAL"},
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{IGC_TDBAH(0), "TDBAH"},
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{IGC_TDLEN(0), "TDLEN"},
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{IGC_TDH(0), "TDH"},
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{IGC_TDT(0), "TDT"},
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{IGC_TXDCTL(0), "TXDCTL"},
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{IGC_TDFH, "TDFH"},
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{IGC_TDFT, "TDFT"},
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{IGC_TDFHS, "TDFHS"},
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{IGC_TDFPC, "TDFPC"},
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/* List Terminator */
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{}
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};
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/* igc_regdump - register printout routine */
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static void igc_regdump(struct igc_hw *hw, struct igc_reg_info *reginfo)
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{
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int n = 0;
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char rname[16];
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u32 regs[8];
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switch (reginfo->ofs) {
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case IGC_RDLEN(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_RDLEN(n));
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break;
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case IGC_RDH(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_RDH(n));
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break;
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case IGC_RDT(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_RDT(n));
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break;
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case IGC_RXDCTL(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_RXDCTL(n));
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break;
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case IGC_RDBAL(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_RDBAL(n));
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break;
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case IGC_RDBAH(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_RDBAH(n));
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break;
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case IGC_TDBAL(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_RDBAL(n));
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break;
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case IGC_TDBAH(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_TDBAH(n));
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break;
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case IGC_TDLEN(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_TDLEN(n));
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break;
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case IGC_TDH(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_TDH(n));
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break;
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case IGC_TDT(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_TDT(n));
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break;
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case IGC_TXDCTL(0):
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for (n = 0; n < 4; n++)
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regs[n] = rd32(IGC_TXDCTL(n));
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break;
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default:
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pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
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return;
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}
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snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
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pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
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regs[2], regs[3]);
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}
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/* igc_rings_dump - Tx-rings and Rx-rings */
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void igc_rings_dump(struct igc_adapter *adapter)
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{
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struct net_device *netdev = adapter->netdev;
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struct my_u0 { u64 a; u64 b; } *u0;
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union igc_adv_tx_desc *tx_desc;
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union igc_adv_rx_desc *rx_desc;
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struct igc_ring *tx_ring;
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struct igc_ring *rx_ring;
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u32 staterr;
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u16 i, n;
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if (!netif_msg_hw(adapter))
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return;
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/* Print netdevice Info */
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if (netdev) {
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dev_info(&adapter->pdev->dev, "Net device Info\n");
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pr_info("Device Name state trans_start\n");
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pr_info("%-15s %016lX %016lX\n", netdev->name,
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netdev->state, dev_trans_start(netdev));
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}
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/* Print TX Ring Summary */
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if (!netdev || !netif_running(netdev))
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goto exit;
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dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
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pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
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for (n = 0; n < adapter->num_tx_queues; n++) {
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struct igc_tx_buffer *buffer_info;
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tx_ring = adapter->tx_ring[n];
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buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
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pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
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n, tx_ring->next_to_use, tx_ring->next_to_clean,
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(u64)dma_unmap_addr(buffer_info, dma),
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dma_unmap_len(buffer_info, len),
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buffer_info->next_to_watch,
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(u64)buffer_info->time_stamp);
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}
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/* Print TX Rings */
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if (!netif_msg_tx_done(adapter))
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goto rx_ring_summary;
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dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
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/* Transmit Descriptor Formats
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*
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* Advanced Transmit Descriptor
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* +--------------------------------------------------------------+
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* 0 | Buffer Address [63:0] |
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* +--------------------------------------------------------------+
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* 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
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* +--------------------------------------------------------------+
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* 63 46 45 40 39 38 36 35 32 31 24 15 0
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*/
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for (n = 0; n < adapter->num_tx_queues; n++) {
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tx_ring = adapter->tx_ring[n];
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pr_info("------------------------------------\n");
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pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
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pr_info("------------------------------------\n");
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pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
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for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
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const char *next_desc;
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struct igc_tx_buffer *buffer_info;
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tx_desc = IGC_TX_DESC(tx_ring, i);
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buffer_info = &tx_ring->tx_buffer_info[i];
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u0 = (struct my_u0 *)tx_desc;
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if (i == tx_ring->next_to_use &&
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i == tx_ring->next_to_clean)
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next_desc = " NTC/U";
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else if (i == tx_ring->next_to_use)
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next_desc = " NTU";
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else if (i == tx_ring->next_to_clean)
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next_desc = " NTC";
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else
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next_desc = "";
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pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
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i, le64_to_cpu(u0->a),
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le64_to_cpu(u0->b),
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(u64)dma_unmap_addr(buffer_info, dma),
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dma_unmap_len(buffer_info, len),
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buffer_info->next_to_watch,
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(u64)buffer_info->time_stamp,
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buffer_info->skb, next_desc);
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if (netif_msg_pktdata(adapter) && buffer_info->skb)
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print_hex_dump(KERN_INFO, "",
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DUMP_PREFIX_ADDRESS,
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16, 1, buffer_info->skb->data,
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dma_unmap_len(buffer_info, len),
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true);
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}
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}
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/* Print RX Rings Summary */
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rx_ring_summary:
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dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
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pr_info("Queue [NTU] [NTC]\n");
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for (n = 0; n < adapter->num_rx_queues; n++) {
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rx_ring = adapter->rx_ring[n];
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pr_info(" %5d %5X %5X\n",
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n, rx_ring->next_to_use, rx_ring->next_to_clean);
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}
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/* Print RX Rings */
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if (!netif_msg_rx_status(adapter))
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goto exit;
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dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
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/* Advanced Receive Descriptor (Read) Format
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* 63 1 0
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* +-----------------------------------------------------+
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* 0 | Packet Buffer Address [63:1] |A0/NSE|
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* +----------------------------------------------+------+
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* 8 | Header Buffer Address [63:1] | DD |
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* +-----------------------------------------------------+
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*
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*
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* Advanced Receive Descriptor (Write-Back) Format
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*
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* 63 48 47 32 31 30 21 20 17 16 4 3 0
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* +------------------------------------------------------+
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* 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
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* | Checksum Ident | | | | Type | Type |
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* +------------------------------------------------------+
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* 8 | VLAN Tag | Length | Extended Error | Extended Status |
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* +------------------------------------------------------+
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* 63 48 47 32 31 20 19 0
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*/
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for (n = 0; n < adapter->num_rx_queues; n++) {
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rx_ring = adapter->rx_ring[n];
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pr_info("------------------------------------\n");
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pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
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pr_info("------------------------------------\n");
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pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
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pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
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for (i = 0; i < rx_ring->count; i++) {
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const char *next_desc;
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struct igc_rx_buffer *buffer_info;
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buffer_info = &rx_ring->rx_buffer_info[i];
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rx_desc = IGC_RX_DESC(rx_ring, i);
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u0 = (struct my_u0 *)rx_desc;
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staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
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if (i == rx_ring->next_to_use)
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next_desc = " NTU";
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else if (i == rx_ring->next_to_clean)
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next_desc = " NTC";
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else
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next_desc = "";
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if (staterr & IGC_RXD_STAT_DD) {
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/* Descriptor Done */
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pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
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"RWB", i,
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le64_to_cpu(u0->a),
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le64_to_cpu(u0->b),
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next_desc);
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} else {
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pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
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"R ", i,
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le64_to_cpu(u0->a),
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le64_to_cpu(u0->b),
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(u64)buffer_info->dma,
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next_desc);
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if (netif_msg_pktdata(adapter) &&
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buffer_info->dma && buffer_info->page) {
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print_hex_dump(KERN_INFO, "",
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DUMP_PREFIX_ADDRESS,
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16, 1,
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page_address
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(buffer_info->page) +
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buffer_info->page_offset,
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igc_rx_bufsz(rx_ring),
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true);
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}
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}
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}
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}
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exit:
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return;
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}
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/* igc_regs_dump - registers dump */
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void igc_regs_dump(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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struct igc_reg_info *reginfo;
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/* Print Registers */
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dev_info(&adapter->pdev->dev, "Register Dump\n");
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pr_info(" Register Name Value\n");
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for (reginfo = (struct igc_reg_info *)igc_reg_info_tbl;
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reginfo->name; reginfo++) {
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igc_regdump(hw, reginfo);
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}
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}
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@ -3546,6 +3546,8 @@ static void igc_reset_task(struct work_struct *work)
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adapter = container_of(work, struct igc_adapter, reset_task);
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igc_rings_dump(adapter);
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igc_regs_dump(adapter);
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netdev_err(adapter->netdev, "Reset adapter\n");
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igc_reinit_locked(adapter);
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}
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@ -17,6 +17,11 @@
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/* Internal Packet Buffer Size Registers */
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#define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
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#define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
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#define IGC_TDFH 0x03410 /* Tx Data FIFO Head - RW */
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#define IGC_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
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#define IGC_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
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#define IGC_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
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#define IGC_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
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/* NVM Register Descriptions */
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#define IGC_EERD 0x12014 /* EEprom mode read - RW */
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