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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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platform/x86: mlx-platform: Add mlx-wdt platform driver activation
Add mlx-wdt platform driver activation. Watchdog driver uses the same regmap infrastructure as others Mellanox platform drivers. Specific registers description for watchdog platform data configuration are added to mlx-platform. There are the registers for watchdog timer manipulation, and action setting on watchdog timer expiration. The watchdog action function could be configured to perform one of the following: system reset, setting PWM to full speed or counter increment. Two types of watchdog devices are supported main and auxiliary. These devices are co-exist and each of them could be configured to handle the specific action. Signed-off-by: Michael Shych <michealsh@mellanox.com> Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This commit is contained in:
Vadim Pasternak
Andy Shevchenko
parent
584814af9f
commit
9b9f2f5416
@ -56,6 +56,16 @@
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#define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
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#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
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#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
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#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
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#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8
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#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9
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#define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb
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#define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd
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#define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce
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#define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf
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#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1
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#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2
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#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3
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#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
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#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
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#define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5
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@ -129,6 +139,18 @@
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#define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
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#define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14
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/* Masks and default values for watchdogs */
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#define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)
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#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))
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#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)
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#define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0
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#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
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#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
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#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
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#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30
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#define MLXPLAT_CPLD_WD_MAX_DEVS 2
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/* mlxplat_priv - platform private data
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* @pdev_i2c - i2c controller platform device
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* @pdev_mux - array of mux platform devices
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@ -136,6 +158,7 @@
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* @pdev_led - led platform devices
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* @pdev_io_regs - register access platform devices
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* @pdev_fan - FAN platform devices
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* @pdev_wd - array of watchdog platform devices
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*/
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struct mlxplat_priv {
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struct platform_device *pdev_i2c;
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@ -144,6 +167,7 @@ struct mlxplat_priv {
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struct platform_device *pdev_led;
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struct platform_device *pdev_io_regs;
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struct platform_device *pdev_fan;
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struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS];
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};
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/* Regions for LPC I2C controller and LPC base register space */
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@ -1351,6 +1375,148 @@ static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
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};
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/* Watchdog type1: hardware implementation version1
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* (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems).
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*/
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static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = {
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{
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.label = "action",
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.reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
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.bit = 0,
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},
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{
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.label = "timeout",
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.reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
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.health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
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},
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{
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.label = "ping",
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.reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
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.mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
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.bit = 0,
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},
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{
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.label = "reset",
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.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(6),
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.bit = 6,
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},
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};
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static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = {
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{
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.label = "action",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
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.bit = 4,
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},
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{
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.label = "timeout",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
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.health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
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},
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{
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.label = "ping",
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.reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
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.mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
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.bit = 1,
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},
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};
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static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = {
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{
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.data = mlxplat_mlxcpld_wd_main_regs_type1,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1),
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.version = MLX_WDT_TYPE1,
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.identity = "mlx-wdt-main",
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},
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{
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.data = mlxplat_mlxcpld_wd_aux_regs_type1,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1),
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.version = MLX_WDT_TYPE1,
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.identity = "mlx-wdt-aux",
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},
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};
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/* Watchdog type2: hardware implementation version 2
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* (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140).
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*/
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static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = {
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{
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.label = "action",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
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.bit = 0,
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},
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{
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.label = "timeout",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
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.health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
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},
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{
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.label = "timeleft",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
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},
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{
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.label = "ping",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
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.bit = 0,
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},
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{
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.label = "reset",
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.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(6),
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.bit = 6,
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},
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};
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static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = {
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{
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.label = "action",
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.reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
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.bit = 4,
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},
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{
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.label = "timeout",
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.reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
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.health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
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},
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{
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.label = "timeleft",
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.reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
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},
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{
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.label = "ping",
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.reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
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.bit = 4,
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},
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};
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static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = {
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{
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.data = mlxplat_mlxcpld_wd_main_regs_type2,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2),
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.version = MLX_WDT_TYPE2,
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.identity = "mlx-wdt-main",
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},
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{
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.data = mlxplat_mlxcpld_wd_aux_regs_type2,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2),
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.version = MLX_WDT_TYPE2,
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.identity = "mlx-wdt-aux",
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},
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};
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static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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@ -1373,6 +1539,14 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
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return true;
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@ -1416,6 +1590,16 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
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@ -1473,6 +1657,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
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@ -1500,6 +1688,7 @@ static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {
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{ MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
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{ MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
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{ MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
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{ MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
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};
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struct mlxplat_mlxcpld_regmap_context {
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@ -1549,6 +1738,8 @@ static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
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static struct mlxreg_core_platform_data *mlxplat_led;
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static struct mlxreg_core_platform_data *mlxplat_regs_io;
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static struct mlxreg_core_platform_data *mlxplat_fan;
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static struct mlxreg_core_platform_data
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*mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS];
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static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
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{
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@ -1564,6 +1755,7 @@ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
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mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
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mlxplat_led = &mlxplat_default_led_data;
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mlxplat_regs_io = &mlxplat_default_regs_io_data;
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mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
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return 1;
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};
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@ -1582,6 +1774,7 @@ static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)
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mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
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mlxplat_led = &mlxplat_msn21xx_led_data;
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mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
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mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
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return 1;
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};
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@ -1600,6 +1793,7 @@ static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi)
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mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
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mlxplat_led = &mlxplat_default_led_data;
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mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
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mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
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return 1;
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};
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@ -1618,6 +1812,7 @@ static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi)
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mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
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mlxplat_led = &mlxplat_msn21xx_led_data;
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mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
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mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
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return 1;
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};
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@ -1637,6 +1832,8 @@ static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi)
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mlxplat_led = &mlxplat_default_ng_led_data;
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mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
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mlxplat_fan = &mlxplat_default_fan_data;
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for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
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mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
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return 1;
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};
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@ -1919,15 +2116,33 @@ static int __init mlxplat_init(void)
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}
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}
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/* Add WD drivers. */
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for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) {
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if (mlxplat_wd_data[j]) {
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mlxplat_wd_data[j]->regmap = mlxplat_hotplug->regmap;
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priv->pdev_wd[j] = platform_device_register_resndata(
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&mlxplat_dev->dev, "mlx-wdt",
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j, NULL, 0,
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mlxplat_wd_data[j],
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sizeof(*mlxplat_wd_data[j]));
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if (IS_ERR(priv->pdev_wd[j])) {
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err = PTR_ERR(priv->pdev_wd[j]);
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goto fail_platform_wd_register;
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}
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}
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}
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/* Sync registers with hardware. */
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regcache_mark_dirty(mlxplat_hotplug->regmap);
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err = regcache_sync(mlxplat_hotplug->regmap);
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if (err)
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goto fail_platform_fan_register;
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goto fail_platform_wd_register;
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return 0;
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fail_platform_fan_register:
|
||||
fail_platform_wd_register:
|
||||
while (--j >= 0)
|
||||
platform_device_unregister(priv->pdev_wd[j]);
|
||||
if (mlxplat_fan)
|
||||
platform_device_unregister(priv->pdev_fan);
|
||||
fail_platform_io_regs_register:
|
||||
@ -1953,6 +2168,8 @@ static void __exit mlxplat_exit(void)
|
||||
struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
|
||||
int i;
|
||||
|
||||
for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--)
|
||||
platform_device_unregister(priv->pdev_wd[i]);
|
||||
if (priv->pdev_fan)
|
||||
platform_device_unregister(priv->pdev_fan);
|
||||
if (priv->pdev_io_regs)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user