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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'perf/updates' into aarch64/for-next/core
Merge in arm64 perf updates: * xgene system PMUv3 support * 16-bit events for ARMv8.1
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commit
9ad95c46c1
@ -552,7 +552,7 @@ static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
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return 0;
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}
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static struct of_device_id armv6_pmu_of_device_ids[] = {
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static const struct of_device_id armv6_pmu_of_device_ids[] = {
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{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
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{.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
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{.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
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@ -529,7 +529,7 @@ static struct attribute_group armv8_pmuv3_events_attr_group = {
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.is_visible = armv8pmu_event_attr_is_visible,
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};
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PMU_FORMAT_ATTR(event, "config:0-9");
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PMU_FORMAT_ATTR(event, "config:0-15");
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static struct attribute *armv8_pmuv3_format_attrs[] = {
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&format_attr_event.attr,
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@ -3,9 +3,10 @@
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#
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menu "Performance monitor support"
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depends on PERF_EVENTS
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config ARM_PMU
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depends on PERF_EVENTS && (ARM || ARM64)
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depends on ARM || ARM64
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bool "ARM PMU framework"
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default y
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help
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@ -18,7 +19,7 @@ config ARM_PMU_ACPI
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config QCOM_L2_PMU
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bool "Qualcomm Technologies L2-cache PMU"
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depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI
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depends on ARCH_QCOM && ARM64 && ACPI
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help
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Provides support for the L2 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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@ -27,7 +28,7 @@ config QCOM_L2_PMU
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config QCOM_L3_PMU
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bool "Qualcomm Technologies L3-cache PMU"
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depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI
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depends on ARCH_QCOM && ARM64 && ACPI
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select QCOM_IRQ_COMBINER
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help
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Provides support for the L3 cache performance monitor unit (PMU)
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@ -36,7 +37,7 @@ config QCOM_L3_PMU
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monitoring L3 cache events.
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config XGENE_PMU
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depends on PERF_EVENTS && ARCH_XGENE
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depends on ARCH_XGENE
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bool "APM X-Gene SoC PMU"
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default n
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help
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