arm64: dt: ZynqMP DT fixes for v5.8

- Add AES mode and fix GIC node
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXtDEmwAKCRDKSWXLKUoM
 IdGtAJ99Y8+O/OOmzkcbenI8+j5hP70nPQCfdTTUGTJh5LuMiBc+h3850zRIqYo=
 =Em7u
 -----END PGP SIGNATURE-----

Merge tag 'zynqmp-dt-for-v5.8' of https://github.com/Xilinx/linux-xlnx into arm/dt

arm64: dt: ZynqMP DT fixes for v5.8

- Add AES mode and fix GIC node

* tag 'zynqmp-dt-for-v5.8' of https://github.com/Xilinx/linux-xlnx:
  arm64: zynqmp: Fix GIC compatible property
  arm64: zynqmp: Add Xilinx AES node

Link: https://lore.kernel.org/r/ad25cfb0-156c-9bf6-a7b8-e30a7a859135@monstr.eu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-06-02 20:45:53 +02:00
commit 9ad249abe7

View File

@ -158,6 +158,10 @@ soc_revision: soc_revision@0 {
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
xlnx_aes: zynqmp-aes {
compatible = "xlnx,zynqmp-aes";
};
};
};
@ -185,7 +189,7 @@ amba_apu: amba-apu@0 {
ranges = <0 0 0 0 0xffffffff>;
gic: interrupt-controller@f9010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
compatible = "arm,gic-400";
#interrupt-cells = <3>;
reg = <0x0 0xf9010000 0x10000>,
<0x0 0xf9020000 0x20000>,